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PDF AD9880 Data sheet ( Hoja de datos )
| Número de pieza | AD9880 | |
| Descripción | Analog/HDMI Dual Display Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9880 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead LQFP Pb-free package
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI v 1.1, DVI v 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
(HDCP 1.1)
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TV
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9880 offers designers the flexibility of an analog interface
and high definition multimedia interface (HDMI) receiver inte-
grated on a single chip. Also included is support for high band-
width digital content protection (HDCP).
Analog Interface
The AD9880 is a complete 8-bit 150 MSPS monolithic analog inter-
face optimized for capturing component video (YPbPr) and RGB
graphics signals. Its 150 MSPS encode rate capability and full power
analog bandwidth of 330 MHz supports all HDTV formats (up to
1080 p) and FPD resolutions up to SXGA (1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with internal
1.25 V reference, a phase-locked loop (PLL), and programmable
gain, offset, and clamp control. The user provides only 1.8 V and
3.3 V power supplies, analog input, and Hsync. Three-state
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Analog/HDMI
Dual Display Interface
AD9880
FUNCTIONAL BLOCK DIAGRAM
R/G/B OR YPbPrIN0
R/G/B OR YPbPrIN1
ANALOG INTERFACE
2:1
MUX
CLAMP
R/G/B 8X3
A/D
or YCbCr
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
SCL
SDA
RX0+
RX0–
RX1+
RX1–
RX2+
RX2–
RXC+
RXC–
RTERM
MCL
MDA
DDCSCL
DDCSDA
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
HDMI RECEIVER
R/G/B 8X3
OR YCbCr
2 DATACK
DE
HSYNC
VSYNC
4
HDCP
R/G/B 8X3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
SOGOUT
DE
SPDIF OUT
8-CHANNEL
I2S OUT
SCLK
MCLK
LRCLK
AD9880
Figure 1.
CMOS outputs can be powered from 1.8 V to 3.3 V. The
AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
Digital Interface
The AD9880 contains a HDMI 1.1-compatible receiver and sup-
ports all HDTV formats (up to 1080 p and 720 p) and display
resolutions up to SXGA (1280 × 1024 @75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive encrypted
video content. The AD9880 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renewa-
bility of the authentication during transmission, as specified by the
HDCP v 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9880 is provided
in a space-saving, 100-lead LQFP surface-mount Pb-free plastic
package and is specified over the 0°C to 70°C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9880
Parameter
VDD Supply Voltage
PVDD Supply Voltage
ID Supply Current (VD)
IDVDD Supply Current (DVDD)
IDD Supply Current (VDD)2
IPVDD Supply Current (PVDD)
Total Power
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full
Power
Signal–to–Noise Ratio (SNR)
Without Harmonics
fIN = 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θJA-Junction-to-Ambient
Temp
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Test Level
IV
IV
VI
VI
VI
VI
VI
VI
Min
1.7
1.7
AD9880KSTZ-100
Typ Max
3.3 3.47
1.8 1.9
260 300
45 60
37 1003
10 15
1.1 1.4
130
25°C V
25°C I
Full V
330
46
45
Full V
60
V 35
1 Drive strength = high.
2 DATACK load = 15 pF, data load = 5 pF.
3 Specified current and power values with a worst case pattern (on/off).
AD9880KSTZ-150
Min Typ Max
1.7 3.3 3.47
1.7 1.8 1.9
330
85
1303
20
1.15 1.4
130
330
46
45
60
35
Unit
V
V
mA
mA
mA
W
mW
MHz
dB
dB
dBc
°C/W
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 2.
Parameter
RESOLUTION
DC DIGITAL I/O Specifications
High-Level Input Voltage, (VIH)
Low-Level Input Voltage, (VIL)
High-Level Output Voltage, (VOH)
Low-Level Output Voltage, (VOL)
DC SPECIFICATIONS
Output High Level
(IOHD) (VOUT = VOH)
Output Low Level
IOLD, (VOUT = VOL)
DATACK High Level
VOHC, (VOUT = VOH)
DATACK Low Level
VOLC, (VOUT = VOL)
Differential Input Voltage, Single Ended
Amplitude
Test
Level
VI
VI
VI
VI
IV
IV
IV
IV
IV
IV
IV
IV
IV
Conditions
Output drive = high
Output drive = low
Output drive = high
Output drive = low
Output drive = high
Output drive = low
Output drive = high
Output drive = low
AD9880KSTZ-100 AD9880KSTZ-150
Min Typ Max Min Typ Max Unit
8 8 Bit
2.5
VDD − 0.1
VDD − 0.1
2.5
0.8
0.1
V
0.8 V
V
0.1 V
36 36 mA
24 24 mA
12 12 mA
8 8 mA
40 40 mA
20 20 mA
30 30 mA
15 15 mA
75
700 75
700 mV
Rev. 0 | Page 4 of 64
5 Page 
AD9880
Pin
PWRDN
FILT
OUTPUTS
HSOUT
VSOUT
SOGOUT
O/E FIELD
SERIAL PORT
SDA
SCL
DDCSDA
DDCSCL
MDA
MCL
DATA OUTPUTS
Red [7:0]
Green [7:0]
Blue [7:0]
DATA CLOCK
OUTPUT
DATACK
Description
Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
External Filter Connection.
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to
this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the section on
PCB Layout Recommendations.
Horizontal Sync Output.
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be
programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.
Vertical Sync Output.
The separated Vsync from a composite signal or a direct pass through of the Vsync signal. The polarity of this output
can be controlled via serial bus bit (Register 0x24 [6]).
Sync-On-Green Slicer Output.
This pin outputs one of four possible signals (controlled by Register 0x1D [1:0]): raw SOG, raw Hsync, regenerated
Hsync from the filter, or the filtered Hsync. See the Sync processing block diagram (see Figure 8) to view how this pin is
connected. (Note: besides slicing off SOG, the output from this pin is not processed on the AD9880. Vsync separation is
performed via the sync separator.
Odd/Even Field Bit for Interlaced Video. This output will identify whether the current field (in an interlaced signal) is odd
or even. The polarity of this signal is programmable via Register 0x24[4].
Serial Port Data I/O for programming AD9880 registers – I2C address is 0x98.
Serial Port Data Clock for programming AD9880 registers.
Serial Port Data I/O for HDCP communications to transmitter – I2C address is 0x74 or 0x76.
Serial Port Data Clock for HDCP communications to transmitter.
Serial Port Data I/O to EEPROM with HDCP keys – I2C address is 0xA0
Serial Port Data Clock to EEPROM with HDCP keys.
Data Output, Red Channel.
Data Output, Green Channel.
Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is
fixed, but will be different if the color space converter is used. When the sampling time is changed by adjusting the
phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output
clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2×
frequency pixel clock and a 90° phase shifted pixel clock) and they are produced either by the internal PLL clock
generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted
via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register.
When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
Rev. 0 | Page 10 of 64
11 Page | ||
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| PDF Descargar | [ Datasheet AD9880.PDF ] | |
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