PDF AD9883 Data sheet ( Hoja de datos )

Número de pieza	AD9883
Descripción	110 MSPS Analog Interface for Flat Panel Displays
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES 110 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Processing Sync Detect for ”Hot Plugging” Midscale Clamping Power-Down Mode Low Power: 500 mW Typical Composite Sync Applications Require an External Coast APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV 110 MSPS Analog Interface for Flat Panel Displays AD9883 FUNCTIONAL BLOCK DIAGRAM RAIN GAIN BAIN HSYNC COAST CLAMP FILT SCL SDA A0 CLAMP 8 A/D ROUTA CLAMP 8 A/D GOUTA CLAMP 8 A/D SYNC PROCESSING AND CLOCK GENERATION SERIAL REGISTER AND POWER MANAGEMENT REF AD9883 BOUTA MIDSCV DTACK HSOUT VSOUT SOGOUT REF BYPASS GENERAL DESCRIPTION The AD9883 is a complete 8-bit, 110 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 110 MSPS encode rate capability and full-power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 × 1024 at 60 Hz). The AD9883 includes a 110 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883’s on-chip PLL generates a pixel clock from HSYNC and COAST inputs. Pixel clock output frequencies range from 12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at 110 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC and Clock output phase relationships are maintained. The AD9883 also offers full sync processing for composite sync and sync-on- green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully pro- grammable via a two-wire serial interface. Fabricated in an advanced CMOS process, the AD9883 is provided in a space-saving 80-lead LQFP surface mount plastic package and is specified over the 0°C to 70°C temperature range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 page PIN CONFIGURATION AD9883 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 GND 1 GREEN <7> 2 GREEN <6> 3 GREEN <5> 4 GREEN <4> 5 GREEN <3> 6 GREEN <2> 7 GREEN <1> 8 GREEN <0> 9 GND 10 VDD 11 BLUE <7> 12 BLUE <6> 13 BLUE <5> 14 BLUE <4> 15 BLUE <3> 16 BLUE <2> 17 BLUE <1> 18 BLUE <0> 19 GND 20 PIN 1 IDENTIFIER AD9883 TOP VIEW (Not to Scale) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 GND 59 VD 58 REF BYPASS 57 SDA 56 SCL 55 A0 54 RAIN 53 GND 52 VD 51 VD 50 GND 49 SOGIN 48 GAIN 47 GND 46 VD 45 VD 44 GND 43 BAIN 42 VD 41 GND NC = NO CONNECT Table I. Complete Pinout List Pin Type Inputs Outputs References Power Supply Control Mnemonic Function RAIN GAIN BAIN HSYNC VSYNC SOGIN CLAMP COAST Analog Input for Converter R Analog Input for Converter G Analog Input for Converter B Horizontal SYNC Input Vertical SYNC Input Input for Sync-on-Green Clamp Input (External CLAMP Signal) PLL COAST Signal Input Red [7:0] Green [7:0] Blue [7:0] DATACK HSOUT VSOUT SOGOUT Outputs of Converter “Red,” Bit 7 Is the MSB Outputs of Converter “Green,” Bit 7 Is the MSB Outputs of Converter “Blue,” Bit 7 Is the MSB Data Output Clock HSYNC Output Clock (Phase-Aligned with DATACK) VSYNC Output Clock (Phase-Aligned with DATACK) Sync on Green Slicer Output REF BYPASS Internal Reference Bypass MIDSCV Internal Midscale Voltage Bypass FILT Connection for External Filter Components for Internal PLL VD VDD PVD GND Analog Power Supply Output Power Supply PLL Power Supply Ground SDA SCL A0 Serial Port Data I/O Serial Port Data Clock (100 kHz Maximum) Serial Port Address Input 1 Value 0.0 V to 1.0 V 0.0 V to 1.0 V 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 1.25 V ± 10% 3.3 V ± 10% 3.3 V ± 10% 3.3 V ± 10% 0V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS Pin Number 54 48 43 30 31 49 38 29 70–77 2–9 12–19 67 66 64 65 58 37 33 57 56 55 REV. 0 –5– 5 Page AD9883 Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard VGA SVGA XGA SXGA Resolution 640 × 480 800 × 600 1024 × 768 1280 × 1024 Refresh Rate 60 Hz 72 Hz 75 Hz 85 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 70 Hz 75 Hz 80 Hz 85 Hz 60 Hz Horizontal Frequency 31.5 kHz 37.7 kHz 37.5 kHz 43.3 kHz 35.1 kHz 37.9 kHz 48.1 kHz 46.9 kHz 53.7 kHz 48.4 kHz 56.5 kHz 60.0 kHz 64.0 kHz 68.3 kHz 64.0 kHz Pixel Rate 25.175 MHz 31.500 MHz 31.500 MHz 36.000 MHz 36.000 MHz 40.000 MHz 50.000 MHz 49.500 MHz 56.250 MHz 65.000 MHz 75.000 MHz 78.750 MHz 85.500 MHz 94.500 MHz 108.000 MHz VCORNGE 00 00 00 00 00 01 01 01 01 01 10 10 10 10 10 CURRENT 101 110 110 110 110 100 100 100 101 110 100 100 100 100 110 Timing The following timing diagrams show the operation of the AD9883. The Output Data Clock signal is created so that its rising edge always occurs between data transitions, and can be used to latch the output data externally. There is a pipeline in the AD9883, which must be flushed before valid data becomes available. This means four data sets are presented before valid data is available. t PER t CYCLE DATACK DATA HSOUT t SKEW Figure 7. Output Timing Hsync Timing Horizontal Sync (Hsync) is processed in the AD9883 to elimi- nate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to Hsync, through a full 360° in 32 steps via the Phase Adjust register (to optimize the pixel sampling time). Display systems use Hsync to align memory and display write cycles, so it is important to have a stable timing relationship between Hsync output (HSOUT) and data clock (DATACK). Three things happen to Horizontal Sync in the AD9883. First, the polarity of Hsync input is determined and will thus have a known output polarity. The known output polarity can be pro- grammed either active high or active low (register 0EH, Bit 5). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via regis- ter 07H. HSOUT is the sync signal that should be used to drive the rest of the display system. RGBIN P0 P1 P2 P3 P4 P5 P6 P7 HSYNC PxCK HS ADCCK 5-PIPE DELAY DATACK DOUTA HSOUT D0 D1 D2 D3 D4 D5 D6 D7 VARIABLE DURATION Figure 8. Timing Diagram REV. 0 –11– 11 Page

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