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PDF HT46R62 Data sheet ( Hoja de datos )
| Número de pieza | HT46R62 | |
| Descripción | A/D with LCD Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT46R62/HT46C62
A/D with LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0047E An PWM application example using the HT46 series of MCUs
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 20 bidirectional I/O lines
(PA, PB0~PB5, PD0~PD2, PD4~PD6)
· Two external interrupt input
· One 8-bit programmable timer/event counter with
PFD (programmable frequency divider) function
· LCD driver with 20´3 or 19´4 segments
(logical output option for SEG0~SEG15)
· 2K´14 program memory
· 88´8 data memory RAM
· Supports PFD for sound generation
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 6-level subroutine nesting
· 6 channels 9-bit resolution A/D converter
· 3-channel 8-bit PWM output shared with 3 I/O lines
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· Low voltage reset/detector function
· 52-pin QFP, 56-pin SSOP packages
General Description
The HT46R62/HT46C62 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C62 is fully pin and
functionally compatible with the OTP version HT46R62
device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
Rev. 1.60
1 July 14, 2005
1 page  
HT46R62/HT46C62
D.C. Characteristics
Ta=25°C
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
¾ fSYS=4MHz
¾ fSYS=8MHz
IDD1
Operating Current
(Crystal OSC, RC OSC)
3V No load, ADC Off,
5V fSYS=4MHz
IDD2
Operating Current
(Crystal OSC, RC OSC)
IDD3
Operating Current
(fSYS=32768Hz)
5V
No load, ADC Off,
fSYS=8MHz
3V
No load, ADC Off
5V
ISTB1
Standby Current
(*fS=T1)
3V No load, system HALT,
5V LCD Off at HALT
ISTB2
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
5V LCD On at HALT, C type
ISTB3
Standby Current
(*fS=WDT OSC)
3V No load, system HALT,
5V LCD On at HALT, C type
ISTB4
Standby Current
(*fS=RTC OSC)
3V
No load, system HALT,
LCD On at HALT, R type,
5V
1/2 bias, VLCD=VDD
(Low bias current option)
ISTB5
Standby Current
(*fS=RTC OSC)
3V
No load, system HALT,
LCD On at HALT, R type,
5V
1/3 bias, VLCD=VDD
(Low bias current option)
ISTB6
Standby Current
(*fS=WDT OSC)
3V
No load, system HALT,
LCD On at HALT, R type,
5V
1/2 bias, VLCD=VDD
(Low bias current option)
ISTB7
Standby Current
(*fS=WDT OSC)
3V
No load, system HALT,
LCD On at HALT, R type,
5V
1/3 bias, VLCD=VDD
(Low bias current option)
VIL1
Input Low Voltage for I/O Ports,
TMR, INT0, INT1
¾
¾
VIH1
Input High Voltage for I/O Ports,
TMR, INT0, INT1
¾
¾
VIL2
VIH2
VLVR
VLVD
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
Low Voltage Detector Voltage
¾
¾
¾
¾
¾
¾
¾
¾
IOL1
I/O Port Segment Logic Output
Sink Current
3V
VOL=0.1VDD
5V
IOH1
I/O Port Segment Logic Output
Source Current
3V
VOH=0.9VDD
5V
Min.
2.2
3.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
0.7VDD
0
0.9VDD
2.7
3.0
6
10
-2
-5
Typ.
¾
¾
1
3
4
0.3
0.6
¾
¾
2.5
10
2
6
17
34
13
28
14
26
10
19
¾
¾
¾
¾
3.0
3.3
12
25
-4
-8
Max.
5.5
5.5
2
5
8
0.6
1
1
2
5
20
5
10
30
60
25
50
25
50
20
40
0.3VDD
VDD
0.4VDD
VDD
3.3
3.6
¾
¾
¾
¾
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
mA
mA
mA
mA
Rev. 1.60
5 July 14, 2005
5 Page 
HT46R62/HT46C62
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the ROM. Only the contents of the pro-
gram counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
External interrupts are triggered by a an edge transition
of INT0 or INT1 (option: high to low, low to high, low to
high or high to low), and the related interrupt request flag
(EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well.
After the interrupt is enabled, the stack is not full, and
the external interrupt is active, a subroutine call to loca-
tion 04H or 08H occurs. The interrupt request flag (EIF0
or EIF1) and EMI bits are all cleared to disable other
maskable interrupts.
The internal Timer/Event Counter interrupt is initialized
by setting the Timer/Event Counter interrupt request flag
(TF; bit 6 of INTC0), which is normally caused by a timer
overflow. After the interrupt is enabled, and the stack is
not full, and the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag (TF) is re-
set, and the EMI bit is cleared to disable further interrupts.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further maskable interrupts.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC1), that is caused by a regular real time clock sig-
nal. After the interrupt is enabled, and the stack is not
full, and the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag (RTF) is
reset and the EMI bit is cleared to disable further inter-
rupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are all held until the ²RETI²
instruction is executed or the EMI bit and the related in-
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EEI0
EEI1
ETI
EIF0
EIF1
TF
¾
Function
Control the master (global) interrupt (1=enabled; 0=disabled)
Control the external interrupt 0 (1=enabled; 0=disabled)
Control the external interrupt 1 (1=enabled; 0=disabled)
Control the Timer/Event Counter interrupt (1=enabled; 0=disabled)
External interrupt 0 request flag (1=active; 0=inactive)
External interrupt 1 request flag (1=active; 0=inactive)
Internal Timer/Event Counter request flag (1=enable; 0=disable)
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
0
1
2
3, 4
5
6
7
Rev. 1.60
Label
¾
ETBI
ERTI
¾
TBF
RTF
¾
Function
Unused bit, read as ²0²
Control the time base interrupt (1=enabled; 0:disabled)
Control the real time clock interrupt (1=enabled; 0:disabled)
Unused bit, read as ²0²
Time base request flag (1=active; 0=inactive)
Real time clock request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC1 (1EH) Register
11
July 14, 2005
11 Page | ||
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| PDF Descargar | [ Datasheet HT46R62.PDF ] | |
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