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PDF HT46R64 Data sheet ( Hoja de datos )
| Número de pieza | HT46R64 | |
| Descripción | A/D with LCD Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT46R64/HT46C64
A/D with LCD Type 8-Bit MCU
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 24 bidirectional I/O lines
· Two external interrupt input
· One 8-bit and one 16-bit programmable timer/event
counter with PFD (programmable frequency divider)
function
· LCD driver with 33´3 or 32´4 segments
(logical output option for SEG0~SEG15)
· 4K´15 program memory
· 192´8 data memory RAM
· Supports PFD for sound generation
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 8-level subroutine nesting
· 8 channels 10-bit resolution A/D converter
· 4-channel 8-bit PWM output shared with 4 I/O lines
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· Low voltage reset/detector function
· 56-pin SSOP, 100-pin QFP package
General Description
The HT46R64/HT46C64 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C64 is fully pin and
functionally compatible with the OTP version HT46R64
device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
HT46C64 under development, available in 4Q, 2004.
Rev. 1.40
1 September 21, 2004
1 page  
HT46R64/HT46C64
D.C. Characteristics
Ta=25°C
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
¾ fSYS=4MHz
¾ fSYS=8MHz
IDD1
Operating Current
(Crystal OSC)
3V No load, ADC off
5V fSYS=4MHz
IDD2
Operating Current
(RC OSC)
3V No load, ADC off
5V fSYS=4MHz
IDD3
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current
(fSYS=32768Hz)
5V
No load, ADC off
fSYS=8MHz
3V
No load, ADC off
5V
ISTB1
Standby Current
(*fS=T1)
3V No load, system HALT
5V LCD off at HALT
ISTB2
Standby Current
(*fS=32.768kHz OSC)
3V No load, system HALT
5V LCD on at HALT, C type
ISTB3
Standby Current
(*fS=WDT RC OSC)
3V No load, system HALT
5V LCD on at HALT, C type
ISTB4
Standby Current
(*fS=32.768kHz OSC)
3V
No load, system HALT
LCD on at HALT, R type,
1/2 bias, VLCD=VDD
5V (Low bias current option)
ISTB5
Standby Current
(*fS=32.768kHz OSC)
3V
No load, system HALT
LCD on at HALT, R type,
1/3 bias, VLCD=VDD
5V (Low bias current option)
ISTB6
Standby Current
(*fS=WDT RC OSC)
3V
No load, system HALT
LCD on at HALT, R type,
1/2 bias, VLCD=VDD
5V (Low bias current option)
ISTB7
Standby Current
(*fS=WDT RC OSC)
3V
No load, system HALT
LCD on at HALT, R type,
1/3 bias, VLCD=VDD
5V (Low bias current option)
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
VIL2
VIH2
VLVR
VLVD
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
Low Voltage Detector Voltage
¾
¾
¾
¾
¾
¾
¾
¾
IOL
I/O Port Segment Logic Output
Sink Current
3V
VOL=0.1VDD
5V
Min.
2.2
3.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
0.7VDD
0
0.9VDD
2.7
3.0
6
10
Typ.
¾
¾
1
3
1
3
4
0.3
0.6
¾
¾
2.5
10
2
6
17
34
13
28
14
26
10
19
¾
¾
¾
¾
3.0
3.3
12
25
Max.
5.5
5.5
2
5
2
5
8
0.6
1
1
2
5
20
5
10
30
60
25
50
25
50
20
40
0.3VDD
VDD
0.4VDD
VDD
3.3
3.6
¾
¾
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
mA
mA
Rev. 1.40
5 September 21, 2004
5 Page 
HT46R64/HT46C64
Once an interrupt subroutine is serviced, other inter-
rupts except NMI are all blocked (by clearing the EMI
bit). This scheme may prevent any further interrupt nest-
ing. Other interrupt requests may take place during this
interval, but only the interrupt request flag will be re-
corded. If a certain interrupt requires servicing within the
service routine, the EMI bit and the corresponding bit of
the INTC0 or of INTC1 may be set in order to allow inter-
rupt nesting. Once the stack is full, the interrupt request
(except NMI) will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack should be pre-
vented from becoming full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the PC onto the stack followed
by a branch to a subroutine at the specified location in
the ROM. Only the contents of the PC is pushed onto
the stack. If the contents of the register or of the status
register (STATUS) is altered by the interrupt service pro-
gram which corrupts the desired control sequence, the
contents should be saved in advance.
External interrupts are triggered by a an edge transition
of INT0 or INT1 (ROM code option: high to low, low to
high, low to high or high to low), and the related interrupt
request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0)
is set as well. After the interrupt is enabled, the stack is
not full, and the external interrupt is active, a subroutine
call to location 04H or 08H occurs. The interrupt request
flag (EIF0 or EIF1) and EMI bits are all cleared to disable
other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 6 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 4 of
INTC1) and its subroutine call location is 10H.
The A/D converter Interrupt is a Non-maskable interrupt
(NMI) which occurs when an A/D conversion process
has been completed and EOCB becomes ²0². The A/D
converter interrupt is controlled by an EADI (bit 7 of the
INTC0). When EADI=²1², the A/D converter interrupt is
enabled. If the EADI=²0², the A/D converter interrupt is
disabled. The A/D converter interrupt cannot be masked
by disabling the EMI. After the interrupt is enabled, and if
the A/D Conversion process has been completed (when
EOCB becomes ²0²), a subroutine call to location 1CH
occurs. If the stack is and if the A/D converter interrupt
subroutine is serviced, the A/D converter interrupt¢s re-
turn address will be pushed into the stack, and the first
return address in the stack will be flushed. It is important
that at least one stack level is left available when using
the A/D interrupt.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
Register
INTC0
(0BH)
INTC1
(1EH)
Bit No.
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Label
EMI
EEI0
EEI1
ET0I
EIF0
EIF1
T0F
EADI
ET1I
ETBI
ERTI
¾
T1F
TBF
RTF
¾
Function
Control the master (global) interrupt (1=enabled; 0=disabled)
Control the external interrupt 0 (1=enabled; 0=disabled)
Control the external interrupt 1 (1=enabled; 0=disabled)
Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
External interrupt 0 request flag (1=active; 0=inactive)
External interrupt 1 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Control the A/D converter interrupt (NMI; 1=enable; 0=disable)
Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
Control the time base interrupt (1=enabled; 0:disabled)
Control the real time clock interrupt (1=enabled; 0:disabled)
Unused bit, read as ²0²
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Time base request flag (1=active; 0=inactive)
Real time clock request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC Register
Rev. 1.40
11 September 21, 2004
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet HT46R64.PDF ] | |
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