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PDF CS5530 Data sheet ( Hoja de datos )
| Número de pieza | CS5530 | |
| Descripción | 24-Bit ADC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5530
24-bit ADC with Ultra-low-noise Amplifier
Features & Description
Chopper-stabilized Instrumentation
Amplifier, 64X
• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)
• 1200 pA Input Current
Digital Gain Scaling up to 40x
Delta-sigma Analog-to-digital Converter
• Linearity Error: 0.0015% FS
• Noise Free Resolution: Up to 19 bits
Scalable VREF Input: Up to Analog Supply
Simple Three-wire Serial Interface
• SPI™ and Microwire™ Compatible
• Schmitt-trigger on Serial Clock (SCLK)
Onboard Offset and Gain Calibration
Registers
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
• VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5530 is a highly integrated ΔΣ Analog-to-Digital
Converter (ADC) which uses charge-balance techniques
to achieve 24-bit performance. The ADC is optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADC includes
a very-low-noise, chopper-stabilized instrumentation
amplifier (12 nV/√Hz @ 0.1 Hz) with a gain of 64X. This
device also includes a fourth-order ΔΣ modulator fol-
lowed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADC and a micro-
controller, the converter includes a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options make this device an ideal
solution for weigh scale and process control
applications.
ORDERING INFORMATION
See page 35.
VA+ C1
C2
VREF+ VREF-
VD+
AIN1+
AIN1-
64X
DIFFERENTIAL
4TH ORDER ΔΣ
MODULATOR
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
CS
SDI
SDO
SCLK
VA-
http://www.cirrus.com
LATCH
A0 A1
CLOCK
GENERATOR
OSC1 OSC2
CALIBRATION
SRAM/CONTROL
LOGIC
DGND
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
NOV ‘09
DS742F3
1 page  
CS5530
ANALOG CHARACTERISTICS (Continued)
(See Notes 1 and 2.)
Parameter
Min
Analog Input
Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode (VA-) + 1.6
CVF Current on AIN+ or AIN-
-
Input Current Noise
-
Open Circuit Detect Current
100
Common Mode Rejection
DC
50, 60 Hz
-
-
Input Capacitance
-
Voltage Reference Input
Range
(VREF+) - (VREF-)
1
CVF Current
(Note 5, 6)
-
Common Mode Rejection
DC
50, 60 Hz
-
-
Input Capacitance
11
System Calibration Specifications
Full-scale Calibration Range
Bipolar/Unipolar Mode
3
Offset Calibration Range
Bipolar Mode
-100
Offset Calibration Range
Unipolar Mode
-90
Typ Max
Unit
-
1200
1
300
130
120
10
(VA+) - 1.6
-
-
-
-
-
-
V
pA
pA/√Hz
nA
dB
dB
pF
2.5 (VA+)-(VA-)
50 -
120 -
120 -
- 22
V
nA
dB
dB
pF
- 110 %FS
- 100 %FS
- 90 %FS
Notes: 5. See the section of the data sheet which discusses input models.
6. Input current on VREF+ or VREF- may increase to 250 nA if operated within 50 mV of VA+ or VA-. This
is due to the rough charge buffer being saturated under these conditions.
DS742F3
5
5 Page 
CS5530
2. GENERAL DESCRIPTION
The CS5530 is a ΔΣ Analog-to-Digital Converter
(ADC) which uses charge-balance techniques to
achieve 24-bit performance. The ADC is optimized
for measuring low-level unipolar or bipolar signals
in weigh scale, process control, scientific, and med-
ical applications.
To accommodate these applications, the ADC in-
cludes a very-low-noise, chopper-stabilized instru-
mentation amplifier (12 nV/√Hz @ 0.1 Hz) with a
gain of 64X. This ADC also includes a fourth-order
ΔΣ modulator followed by a digital filter which pro-
vides twenty selectable output word rates of 6.25,
7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 samples
per second (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a
micro-controller, the converters include a simple
three-wire serial interface which is SPI and Mi-
crowire compatible with a Schmitt-trigger input on
the serial clock (SCLK).
2.1 Analog Input
Figure 3 illustrates a block diagram of the CS5530.
The front end includes a chopper-stabilized instru-
mentation amplifier with a gain of 64X.
The amplifier is chopper-stabilized and operates with
a chop clock frequency of MCLK/128. The CVF
(sampling) current into the instrumentation amplifier
is typically 1200 pA over
-40°C to +85°C
(MCLK=4.9152 MHz). The common-mode plus sig-
nal range of the instrumentation amplifier is (VA-) +
1.6 V to (VA+) - 1.6 V.
Figure 4 illustrates the input model for the 64X am-
plifier.
AIN
Vos ≤ 8 mV
in = fVos C
C = 3 .9 pF
f=
MCLK
128
Figure 4. Input Model for AIN+ and AIN- Pins
Note:
The C = 3.9 pF capacitor is for input current
modeling only. For physical input capacitance
see ‘Input Capacitance’ specification under
Analog Characteristics.
VREF+ VREF-
X1 X1
AIN+
AIN-
1000 Ω
64x
22 nF
C1 PIN
C2 PIN
Differential
4th Order
Sinc 5
ΔΣ Digital
Modulator Filter
1000 Ω
Programmable
Sinc 3
Digital Filter
Serial
Port
Figure 3. Front End Configuration
DS742F3
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5530.PDF ] | |
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