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PDF MB15F73UV Data sheet ( Hoja de datos )
| Número de pieza | MB15F73UV | |
| Descripción | Dual Serial Input PLL Frequency Synthesizer | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21376-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F73UV
s DESCRIPTION
The Fujitsu MB15F73UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250 MHz and
a 600 MHz prescalers. A 64/65 or a 128/129 for the 2250 MHz prescaler, and a 8/9 or a 16/17 for the 600 MHz
prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 3.2 mA at 2.7 V. The supply voltage range
is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial data. The data format is the same as the previous one MB15F03SL, MB15F73SP/UL. Fast
locking is achieved for adopting the new circuit.
MB15F73UV is in the new small package (BCC18), which decreases a mount area of MB15F73UV about 50%
comparing with the former BCC20 (for dual PLL) .
MB15F73UV is ideally suited for wireless mobile communications, such as CDMA and PCS.
s FEATURES
• High frequency operation
: RF synthesizer : 2250 MHz Max
: IF synthesizer : 600 MHz Max
• Low power supply voltage
: VCC = 2.4 V to 3.6 V
• Ultra low power supply current : ICC = 3.2 mA Typ
(VCC = 2.7 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)
s PACKAGES
(Continued)
18-pin plastic BCC
(LCC-18P-M05)
1 page  
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MB15F73UV
s ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Min Max
Unit
Power supply voltage
VCC −0.5 4.0
V
Input voltage
VI
−0.5
VCC + 0.5
V
Output voltage
LD/fout
DoIF, DoRF
VO
VDO
GND
GND
VCC
VCC
V
V
Storage temperature
Tstg −55 +125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage
Operating temperature
Symbol
VCC
VI
Ta
Min
2.4
GND
−40
Value
Typ
2.7
Max
3.6
VCC
+85
Unit
V
V
°C
Remarks
VCCRF = VCCIF
Notes : • VCCRF, VCCIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VCCIF to keep
them equal.
It is recommended that the non-use PLL is controlled by power saving function.
• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the following precautions when handling the device.
• When storing and transporting the device, put it in a conductive case.
• Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as
well as yourself. Use a conductive sheet on working bench.
• Before fitting the device into or removing it from the socket, turn the power supply off.
• When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
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MB15F73UV
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PS pin
Normal mode
H
Power saving mode
L
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes : • When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
• Serial data input are done after the power supply becomes stable, and then the power saving mode is
released after completed the data input.
VCC
Clock
Data
LE
PS
OFF
ON
tV ≥ 1 µs
tPS ≥ 100 ns
(1) (2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data at least 1 µs after the power supply becomes stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PSIF, PSRF : “L” → “H”) at least 100 ns later after setting serial data.
11
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet MB15F73UV.PDF ] | |
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