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PDF MB15F73UL Data sheet ( Hoja de datos )
| Número de pieza | MB15F73UL | |
| Descripción | ASSP Dual Serial Input PLL Frequency Synthesizer | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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www.DataSheet4U.com
Dec. 2000
Edition 2.0
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F73UL
n DESCRIPTION
The Fujitsu MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250MHz and a
600MHz prescalers. A 64/65 or a 128/129 for the 2250MHz prescaler, and a 8/9 or a 16/17 for the 600MHz prescaler
can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process is used, as a result a supply current is typically 3.2mA typ. at 2.7V. The supply voltage
range is from 2.4V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA
selectable by serial data. The data format is same as the previous one MB15F03SL, MB15F73SP. Fast locking is
acheived for adopting the new circuit.
The new package(BCC20) decreases a mount area of MB15F73UL more than 30% comparing with the former
BCC16(for dual PLL).
MB15F73UL is ideally suited for wireless mobile communications, such as GSM and CDMA.
n FEATURES
• High frequency operation: RF synthesizer : 2250MHz max
IF synthesizer : 600MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current : ICC = 3.2 mA typ. (VCC = Vp=2.7V, Ta=25°C, SW=0 in RF, IF locking state)
• Direct power saving function : Power supply current in power saving mode
ry.Typ. 0.1 µA(Vcc=Vp=2.7V, Ta=25°C), Max. 10 µA(Vcc=Vp=2.7V)
• Dual modulus prescaler : 2250MHz prescaler(64/65 or 128/129) / 600MHz prescaler(8/9 or 16/17)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
a• Serial input programmable divider consisting of:
in- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
lim• On-chip phase comparator for fast lock and low noise
re• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to 85°C
P• Sireal data format compatible with MB15F03SL
20-pin, Plastic TSSOP
20-pad, Plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)
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1 page  
www.DataSheet4U.com
Dec. 2000
Edition 2.0
MB15F73UL
n ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
VCC
Vp
VI
VO
VDO
Tstg
Rating
–0.5 to +4.0
Vcc to +4.0
–0.5 to VCC +0.5
GND to Vcc
GND to Vp
–55 to +125
Unit Remark
V
V
V
V LD/fout
V Do
°C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
n RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage
Operating temperature
Symbol
VCC
Vp
VI
Ta
Min.
2.4
Vcc
GND
–40
Value
Typ.
2.7
2.7
–
–
Max.
3.6
3.6
VCC
+85
Unit
V
V
V
°C
Remark
VCCRF = VCCIF
Handling Precautions
(1) VccRF,VpRF,VccIF and VpIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VccRF,VpRF,VccIF and VpIF to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
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5 Page 
www.DataSheet4U.com
Dec. 2000
Edition 2.0
MB15F73UL
Table. 8 Charge Pump Current Setting
CS Current value
1 + 6.0 mA
0 + 1.5 mA
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H Normal mode
L Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode, PS=Low, for at least 1µs.
11
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| PDF Descargar | [ Datasheet MB15F73UL.PDF ] | |
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