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PDF MC74LVX259 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX259 | |
| Descripción | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74LVX259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
With LSTTL−Compatible Inputs
The MC74LVX259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The LVX259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
The MC74LVX259 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5.0 V circuits to
3.0 V circuits.
Features
• High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 VCC
15 RESET
14 ENABLE
13 DATA IN
12 Q7
11 Q6
10 Q5
9 Q4
MARKING DIAGRAMS
16
LVX259G
AWLYWW
1
SOIC−16
16
LVX
259
ALYWG
G
1
TSSOP−16
LVX259 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 4
1
Publication Order Number:
MC74LVX259/D
1 page  
MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
TA = 25°C
−40°C ≤ TA ≤ 85°C
(V) Min Typ Max Min Max Unit
VIH Minimum High−Level
Input Voltage
VIL Maximum Low−Level
Input Voltage
VOH High−Level Output
Voltage
IOH = −50 mA
IOH = −50 mA
IOH = −4 mA
VOL Low−Level Output
Voltage
IOL = 50 mA
IOL = 50 mA
IOL = 4 mA
IIN Input Leakage Current VIN = 5.5 V or GND
ICC Maximum Quiescent
Supply Current
(per package)
VIN = VCC or GND
2.0 0.75 VCC −
3.0 0.7 VCC −
3.6 0.7 VCC −
− 0.75 VCC −
− 0.7 VCC −
− 0.7 VCC −
2.0 − − 0.25 VCC − 0.25 VCC
3.0 − − 0.3 VCC − 0.3 VCC
3.6 − − 0.3 VCC − 0.3 VCC
2.0
1.9 2.0
−
1.9
−
3.0
2.9 3.0
−
2.9
−
3.0 2.58 −
−
2.48
−
2.0 − 0.0 0.1 − 0.1
3.0 − 0.0 0.1 − 0.1
3.0 − − 0.36 − 0.44
0 to 3.6
−
− ±0.1
−
±1.0
3.6 1.0 1.0 2.0
−
−
V
V
V
V
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
Symbol
Parameter
Test Conditions
TA = 25°C
Min Typ Max
−40°C ≤ TA ≤ 85°C
Min Max
Unit
tPLH,
tPHL
Maximum Propagation
Delay, Data to Output
(Figures 4 and 8)
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
−
−
−
−
6.3 9.0
9.0 14.0
5.6 8.0
8.0 12.0
1.0
1.0
1.0
1.0
12.0 ns
15.0
11.0
14.0
tPLH,
tPHL
Maximum Propagation
Delay, Address Select
to Output
(Figures 5 and 8)
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
−
−
−
−
6.3 9.0
9.0 14.0
5.6 8.0
8.0 12.0
1.0
1.0
1.0
1.0
12.0 ns
15.0
11.0
14.0
tPLH,
tPHL
Maximum Propagation
Delay, Enable to Output
(Figures 6 and 8)
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
−
−
−
−
6.3 9.0
9.0 14.0
5.6 9.0
8.0 12.0
1.0
1.0
1.0
1.0
12.0 ns
15.0
11.0
14.0
tPHL Maximum Propogation VCC = 2.7 V
CL = 15pF
Delay, Reset to Output
(Figures 6 and 8)
CL = 50pF
VCC = 3.3 V ± 0.3 V CL = 15pF
CL = 50pF
−
−
−
−
6.3 9.0
9.0 14.0
5.6 9.0
8.0 12.0
1.0
1.0
1.0
1.0
12.0 ns
15.0
11.0
14.0
CIN Maximum Input
Capacitance
− 6 10 −
10 pF
Typical @ 25°C, VCC = 3.3 V
CPD Power Dissipation Capacitance (Note 5)
30 pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
http://onsemi.com
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| PDF Descargar | [ Datasheet MC74LVX259.PDF ] | |
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