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Número de pieza | MC74LVQ573 | |
Descripción | LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage Quiet CMOS
Octal Transparent Latch
Flow Through Pinout
(3-State, Non-Inverting)
The MC74LVQ573 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. The MC74LVQ573
is suitable for TTL level bus oriented applications where a memory
element is required.
The MC74LCX573 contains 8 D–type latches with 3–state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on the D inputs a
setup time preceding the HIGH–to–LOW transition of LE. The 3–state
standard outputs are controlled by the Output Enable (OE) input. When
OE is LOW, the standard outputs are enabled. When OE is HIGH, the
standard outputs are in the high impedance state, but this does not
interfere with new data entering into the latches. The LCX573 flow
through design facilitates easy PC board layout.
• Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low
Noise Applications
• Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
• Guaranteed Skew Specifications
• Guaranteed Incident Wave Switching into 75Ω
• Low Static Supply Current (10µA) Substantially Reduces System Power
Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V
Pinout: 20–Lead (Top View)
VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
MC74LVQ573
LVQ
LOW–VOLTAGE
CMOS OCTAL
TRANSPARENT LATCH
20
1
20
1
20
1
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
PIN NAMES
Pins
Function
OE
LE
D0–D7
O0–O7
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
11/95
© Motorola, Inc. 1995
DataSheet4 U .com
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MC74LVQ573
Dn 50% VCC
tPLH
On
50% VCC
50% VCC
tPHL
50% VCC
WAVEFORM 1 – PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
VCC
0V
VOH
VOL
OE
tPZH
On
50% VCC
tPHZ
50% VCC
50% VCC
tPZL
On
tPLZ
50% VCC
VCC
Dn
0V
VCC
VOH – 0.3V LE 50% VCC
≈ 0V
≈ 3.0V
On
VOL + 0.3V
GND
50% VCC
ts
tw
tPLH, tPHL
50% VCC
VCC
50% VCC
0V
th
VCC
50% VCC
0V
VOH
VOL
WAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
WAVEFORM 3 – LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
Figure 1. AC Waveforms
PULSE
GENERATOR
VCC
DUT
RT
R1
CL RL
2 • VCC
OPEN
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
2 • VCC
Open Collector/Drain tPLH and tPHL
2 • VCC
tPZH, tPHZ
Open
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 2. Test Circuit
ECLinPS and ECLinPS Lite
DataSheetD4LU14.0co—mRev 3
5
MOTOROLA
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet MC74LVQ573.PDF ] |
Número de pieza | Descripción | Fabricantes |
MC74LVQ573 | LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH | Motorola Semiconductors |
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