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PDF SH67L19 Data sheet ( Hoja de datos )
| Número de pieza | SH67L19 | |
| Descripción | 4K 4-Bit Micro Controller | |
| Fabricantes | Sino Wealth Microelectronic | |
| Logotipo |  |
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SH67L19
4K 4-bit Micro-controller with LCD Driver
Features
The SH6610C-based single-chip 4-bit micro-controller
Dual clock sources:
with LCD driver
- OSC: Crystal oscillator: 32.768kHz, RC oscillator:
ROM: 4K X 16 bits
32kHz or 131kHz. (selected by Code Option)
RAM: 256 X 4 bits
- OSCX: Ceramic oscillator: 455kHz, RC oscillator:
Operation Voltage: 1.2V - 1.7V
262kHz or 500kHz (400kHz - 600kHz). (Selected by
4-Level subroutine nesting (include interrupts)
system register)
One 8-bit Timers with pre-divider circuit
Instruction cycle time:
One 8-bit Base Timer
- 122.07µs for 32.768 kHz crystal
Warm-up timer for power-on reset
- 30.53µs for 131 kHz RC
Powerful interrupt sources:
- 8.79µs for 455kHz ceramic
- External interrupts (Falling or rising edge)
- 15.27µs for 262kHz RC
- Timer0 interrupts
- 8µs for 500kHz RC
- Base Timer interrupts
Built-in 2-channel PSG
- PORTB, C interrupts (Falling or rising edge)
24 CMOS bi-directional I/O pins
Built-in alarm generator
DataSheet4U.coBmuilt-in EL-light driver
- PC, PD, PE, PF can switch to segment
Built-in watchdog timer
LCD driver: Up to 6 X 38 dots
Built-in Resistor to Frequency converts circuit
- 1/6 duty, 1/3 bias; 1/5 duty, 1/3 bias; 1/4 duty, 1/3 bias
Two low power operation modes: HALT and STOP
or 1/3 duty, 1/2 bias selected by Code Option
Low power consumption
- 17 segment shared with PORTC, D, E, F and CX
Bonding option for multi-code software
Built-in voltage double and treble charge pump circuit
Available in CHIP FORM
DataShee
General Description
The SH67L19 is a single chip micro-controller integrated with 4K mask ROM, SRAM, timer, PSG, alarm, RFC, EL-light, LCD
driver, I/O ports. This chip builds in a dual-oscillator to enhance the total chip performance.
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3. RAM
Built-in SRAM contains general-purpose data memory, LCD RAM, and system registers. Direct addressing in one instruction
can access them.
The following is the memory allocation map:
$000 - $01F: System register and I/O
$020 - $11F: Data memory (256 X 4bits, divide into 3 banks)
$300 - $325, $330 - $355: LCD RAM
$360 - $368: PSG control registers (9 X 4 bits)
$269 - $26D: R-F counter registers (5 X 4 bit)
The Configuration of System Register
Address
$00
Bit3
IEX
Bit2
IET0
Bit1
IEBT
Bit0 R/W
Remarks
IEP R/W Interrupt enable flags
Initial
Value
0000
$01 IRQX IRQT0 IRQBT IRQP R/W Interrupt request flags
$02 TM0.3 TM0.2 TM0.1 TM0.0 R/W Timer0 mode register
0000
0000
$03 BTM.3 BTM.2 BTM.1 BTM.0 R/W Base timer mode register
0000
$04
T0L.3
T0L.2
T0L.1
T0L.0 R/W Timer0 load/counter low nibble
$05 T0H.3 T0H.2 T0H.1 T0H.0 R/W Timer0 load/counter high nibble
0000
0000
Bit0: PSG on/off control
$06
ENX
ELON
LCDOFF PSGON R/W
Bit1: LCD on/off control
Bit2: EL-light on/off control
Bit3: R-F convert counter on/off control
$07
O/RF
RX3EN
RX2EN
RX1EN
R/W
Bit0 - 2: count resister1 - 3 enable
Bit3: set PORTB as R-F converter
$08
PA.3
PA.2
PA.1
PA.0 R/W PORTA data register
$09
PB.3
PB.2
PB.1
PB.D0 ataSRh/eWet4UP.OcoRmTB data register
$0A
PC.3
PC.2
PC.1
PC.0 R/W PORTC data register
0010
0000
0000
0000
0000
$0B
PD.3
PD.2
PD.1
PD.0 R/W PORTD data register
0000
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE data register
$0D PF.3 PF.2 PF.1 PF.0 R/W PORTF data register
0000
0000
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table branch register
-
$0F
INX.3
INX.2
INX1
INX.0 R/W Index register (INX)
$10
DPL3
DPL2
DPL1
DPL0 R/W Data pointer for INX low nibble
-
-
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble
$12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble
-
-
Bit0: Set CX as LCD segment 38
Bit1: Select LCD segment output high or low
$13 ELF ELPF SOH/L S/CX R/W
EL-LIGHT mode control
0001
Bit2: ELP driver output frequency control
Bit3: EL-LIGHT driver frequency select
Bit0: Heavy Load Mode
$14
OXS
OXM
OXON
HLM
R/W
Bit1: Turn on OSCX oscillator
Bit2: CPU clocks select (1: OSCX /0: OSC)
Bit3: OSCX type selection
0000
DataShee
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8. Programmable Sound Generator (PSG)
PSG has channel1 and channel2. Channel 1 is a 7-bit pseudo random counter. Channel 2 is a 15-bit pseudo random counter.
Mode bits CM1, CM2 determine which of the two counters will be a noise or a tone generator. To reduce power consumption,
disable the sound effect generator during STOP mode. Channel 2 TONE mode is same as Channel 1. (7-bit pseudo-random
counter). PSG also provides alarm function. The alarm on or off controlled by register (ALM). This eliminates some
programming codes.
Address
$360
$361
$362
$363
$364
$365
Bit 3
C1.3
CM1
C2.3
C2.7
C2.11
CM2
$366
$367
$368
VOL1
P2.1
-
Bit 2
C1.2
C1.6
C2.2
C2.6
C2.10
C2.14
VOL0
P2.0
F262
Bit 1
C1.1
C1.5
C2.1
C2.5
C2.9
C2.13
CH2EN
P1.1
ALM
Bit 0
C1.0
C1.4
C2.0
C2.4
C2.8
C2.12
CH1EN
P1.0
SEL
Remarks
PSG channel 1 low nibble
PSG channel 1high nibble
Bit3: channel 1 mode control
PSG channel 2 nibble 1 or alarm output
PSG channel 2 nibble 2
PSG channel 2 nibble 3
PSG channel 2 nibble 4
Bit3: channel 2 mode control
Bit0: Channel 1 enable
Bit1: Channel 2 enable
Bit2, Bit3: volume control (initially 0, no sound)
PSG1 and PSG2 Pre-scalar
Bit0: PSG clock source select.
Bit1: Alarm on or off.
Bit2: OSCX RC oscillator select
R/W
W
W
W
W
W
W
W
W
W
PORTA.1 and PORTA.2 Output Control and Vol. CDoanttaroSlheet4U.com
When PSGON = 1 and ALM=0, the PORTA.1 PORTA.2 is used as PSG output and controlled by the volume control bit into 4
volume levels output. When PSGON = 1 and ALM = 1, the alarm function will open, PORTA.1 PORTA.2 is used as alarm
output.
DataShee
PSGON ALM
Function
0 X PORTA.1 and PORTA.2 as I/O Port
1 0 PORTA.1 and PORTA.2 as PSG output
1 1 PORTA.1 and PORTA.2 as Alarm output
VOL1
0
0
1
1
VOL0
0
1
0
1
Vol. Level
1 (no sound)
2
3
4
PSG Two Channels Mode Control
When using PSG output (PSGON = 1 and ALM = 0), two channels’ mode is controlled by CM1 ($361 bit3), CM2 ($365 bit3):
CM1: 1: channel 1 is noise generator. 0: channel 1 is tone generator.
CM2: 1: channel 2 is noise generator. 0: channel 2 is tone generator.
Channel 1
Channel 1 is constructed by a 7-bit pseudo random counter. Channel 1 is enabled/disabled by CH1EN. It can be a 7-bit
wide-band noise generator or a 7-bit sound generator. It can create either sound frequency by writing value N in C1.6 - C1.0.
Channel 2
Channel 2 is constructed by a 15-bit pseudo random counter. Channel 2 is enabled/disabled by CH2EN. It can be a 15-bit
wide-band noise generator or a 7-bit sound generator. It can create either sound frequency by writing value N in C2.8 - C2.14.
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| PDF Descargar | [ Datasheet SH67L19.PDF ] | |
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