PDF STLC60135 Data sheet ( Hoja de datos )

Número de pieza	STLC60135
Descripción	TOSCA ADSL DMT TRANSCEIVER
Fabricantes	ST Microelectronics
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No Preview Available ! ® STLC60135 TOSCA™ ADSL DMT TRANSCEIVER DTM modem for ADSL, compatible with the following standards: – ANSI T1.413 Issue 2 – ITU-T G.992.1 (G.dmt) – ITU-T G.992.2 (G.lite) Same chip for both ATU-C and ATU-R Supports either ATM (Utopia level 1 & 2) or bit- stream interface 16 bit multiplexed microprocessor interface (lit- tle and big endian compatibility) Analog Front End management Dual latency paths: fast and interleaved ATM’s PHY layer: cell processing (cell deline- ation, cell insertion, HEC) ADSL’s overhead management Reed Solomon encode/decode Trellis encode/decode (Viterbi) DMT mapping/ demapping over 256 carriers Fine (2ppm) timing recover using Rotor and Adaptative Frequency Domain Equalizing Time Domain Equalization Front end digital filters 0.35µm HCMOS6 Technology 144 pin PQFP package Power Consumption 1 Watt at 3.3V Figure 1. Block Diagram TEST SIGNALS PQFP144 ORDERING NUMBER: STLC60135 Applications ATU-C: DSLAM, Routers at Central Office ATU-R: Routers at SOHO, stand-alone mo- dems, PC mother boards General Description The STLC60135 is the DMT modem and ATM framer of the STMicroelectronics Tosca™ chipset. When coupled with STLC60134 analog front-end and an external controller running dedicated firm- ware, the product fulfils ANSI T1.413 “Issue 2” DMT ADSL specification. The STLC60135 may be used at both ends of ADSL loop: ATU-C and ATU-R. The chip sup- ports UTOPIA level 1 and UTOPIA level 2 inter- face and a non ATM synchronous bit-stream in- terface. CLOCK TEST MODULE DATA SYMBOL TIMING UNIT VCXO AFE INTERFACE DSP FRONT-END FFT/IFFT ROTOR TRELLIS CODING MAPPER/ DEMAPPER GENERIC TC REED/ SOLOMON INTERFACE MODULE STM UTOPIA AFE CONTROL September 1999 AFE CONTROL INTERFACE CONTROLLER INTERFACE ATM SPECIFIC TC CONTROLLER BUS GENERAL PURPOSE I/Os D98TL315 1/25 1 page STLC60135 PIN FUNCTIONS (continued) Pin Name Type Supply Driver BS Function 92 SLR_FRAME_S O VDD BT4CR Receive Frame Identifier Interleaved 93 SLR_DATA_S_1 O VDD BT4CR Receive Data Interleave 1 94 SLR_DATA_S_0 O VDD BT4CR Receive Data Interleave 0 95 VDD (VSS + 3.3V) Power Supply 96 SLR_VAL_S O VDD BT4CR Receive Data Valid Indicator Interleaved 97 SLR_DATA_F_1 O VDD BT4CR Receive Data Fast 1 98 SLR_DATA_F_0 O VDD BT4CR Receive Data Fast 0 99 SLR_VAL_F O VDD BT4CR Receive Data Valid Indicator Fast 100 SLAP_CLOCK O VDD BT4CR Clock for SLAP I/F 101 SLT_FRAME_F O VDD BT4CR Transmit Start of frame Indicator Fast 102 VSS 0V Ground 103 SLT_DATA_F_1 I VDD IBUFDQ Transmit Data Fast 1 104 SLT_DATA_F_0 I VDD IBUFDQ Transmit Data Fast 0 105 SLT_DATA_S_1 I VDD IBUFDQ Transmit Data Interleave 1 106 SLT_DATA_S_0 I VDD IBUFDQ Transmit Data Interleave 0 107 SLT_REQ_F O VDD BT4CR Transmit Byte Request Fast 108 VDD (VSS + 3.3V) Power Supply 109 VSS 0V Ground 110 SLT_REQ_S O VDD BT4CR Transmit Byte Request Interleaved 111 STL_FRAME_S O VDD BT4CR Transmit Start of frame Indication Interleaved 112 TDI I-PU VDD IBUFUQ JTAG I/P 113 TDO OZ VDD BT4CR JTAG O/P 114 TMS I-PU VDD IBUFUQ JTAG Made Select 115 VDD (VSS + 3.3V) Power Supply 116 TCK I-PD VDD IBUFDQ JTAG Clock 117 VSS 0V Ground 118 TRSTB I-PD VDD IBUFDQ JTAG Reset 119 TESTSE I VDD IBUF none Enables scan test mode 120 GP_OUT O VDD BD8SCR O General purpose output 121 PDOW N O VDD BT4CR O Power down analog front end (Reset) 122 VDD (VSS + 3.3V) Power Supply 123 AFRXD_0 I VDD IBUF I Receive data nibble 124 AFRXD_1 I VDD IBUF I Receive data nibble 125 AFRXD_2 I VDD IBUF I Receive data nibble 126 AFRXD_3 I VDD IBUF I Receive data nibble 127 VSS 0V Ground 128 CLWD I VDD IBUF I Start of word indication 129 MCLK I VDD IBUF C Master clock 130 CTRLDATA O VDD BT4CR O Serial data Transmit channel 131 VDD (VSS + 3.3V) Power Supply 132 AFTXED_0 O VDD BT4CR O Transmit echo nibble 133 AFTXED_1 O VDD BT4CR O Transmit echo nibble 134 VSS 0V Ground 135 AFTXED_2 O VDD BT4CR O Transmit echo nibble 136 AFTXED_3 O VDD BT4CR O Transmit echo nibble 137 VDD (VSS + 3.3V) Power Supply 138 IDDq I VDD IBUF none Test pin, active high 5/25 5 Page STLC60135 The DSTU schedulers execute a program, con- trolled by program opcodes and a set of vari- ables, the most important of which are real time counters. The transmit and receive sequencers are completely independent and run different pro- grams. An independent set of variables is as- signed to each of them. The sequencer programs can be updated in real time. STLC60135 interfaces Overview Figure 9. STLC60135 interfaces Processor Interface (ATC) The STLC60135 is controlled and configured by an external processor across the processor inter- face. All programmable coefficients and parame- ters are loaded through this path. The ADSL initialization is also controlled by this interface Two interface types are supported; A generic asynchronous interface (i.e. PowerPC or any mi- croprocessor interface) and a specific i960 inter- face. The choice is made by the OBC_TYPE pin. (0 selects i960 type interface, 1 selects generic access). AFE INTERFACE TO ADSL LINE (STLC60134) RESET JTAG CLOCK STLC60135 PROCESSOR INTERFACE (ATC) DIGITAL INTERFACE D98TL368A UTOPIA/BITSTREAM INTERFACE Data and addresses are multiplexed. STLC60135 works in 16 bits data access, so ad- dress bit 0 is not used. Address bit 1 is not multi- plexed with data. It has its own pin : BE1 Byte acces are not supported. Access cycle read or write are always in 16 bits data wide, ie bit ad- dress A0 is always zero value. The interrupt re- quest pin to the processor is INTB, and is an Open Drain output. Tle STLC60135 supports both little and big en- dian. The default feature is big endian. Figure 10. Processor Interface Read cycle i960 mode PCLK Ta Tw Tw Tw Tw Td Tr Ta ALE CSB RDYB Wait AD ADDR DATAin ATC samples data BE1 ADD(1) WR_RDB D98TL324A Figure 11. Processor Interface Write Cycle i960 mode (1): The RDYB output is continuously in tri-state, except for 2 cycles PCLK Ta Tw Tw Tw Tw Td Tr Ta ALE CSB RDYB Wait AD BE1 WR_RDB ADDR DATAout ADD(1) STLC60135 samples data D98TL325A (1): The RDYB output is continuously in tri-state, except for 2 cycles 11/25 11 Page

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