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PDF STLC60134S Data sheet ( Hoja de datos )
| Número de pieza | STLC60134S | |
| Descripción | TOSCA INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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® STLC60134S
TOSCA™ INTEGRATED ADSL CMOS
ANALOG FRONT-END CIRCUIT
FULLY INTEGRATED AFE FOR ADSL
OVERALL 12 BIT RESOLUTION, 1.1MHz
SIGNAL BANDWIDTH
8.8MS/s ADC
8.8MS/s DAC
THD: -60dB @FULL SCALE
4-BIT DIGITAL INTERFACE TO/FROM THE
DMT MODEM
1V FULL SCALE INPUT
DIFFERENTIAL ANALOG I/O
ACCURATE CONTINUOUS-TIME CHANNEL
FILTERING
3rd & 4th ORDER TUNABLE CONTINUOUS
TIME LP FILTERS
0.5 WATT AT 3.3V
0.5µm HCMOS5 LA TECHNOLOGY
64 PIN TQFP PACKAGE
DESCRIPTION
STLC60134S is the Analog Front End of the
STMicroelectronics Tosca™ ADSL chipset and
when coupled with STLC60135 (DTM modem) al-
Figure 1. Block Diagram
TQFP64
ORDERING NUMBER: STLC60134S
lows to get a T1.413 Issue 2 compliant solution.
The STLC60134S analog front end handles 2
transmission channels on a balanced 2 wire inter-
connection; a 16 to 640Kbit/s upstream channel
and a 1.536 to 8.192Mbit/s downstream channel.
A 256 carrier DMT coding (frequency spacing
4.3125kHz) transforms the downstream channel
to a 1MHz bandwidth analog signal (tones 32-
255) and the upstream channel (tones 8-31) to a
100kHz bandwidth signal on the line.
This asymmetrical data transmission system uses
high resolution, high speed analog to digital and
digital to analog conversion and high order ana-
log filtering to reduce the echo and noise in both
TXP
TXN
G=-15...0dB
step=1dB
-+
+-
AGCtx
1.1MHz
HC2
RXP(0:1)
RXN(0:1)
G=0..31dB
step=1dB
AGCrx
R-MOS-C
TUNING
I/V-REF
XTAL-DRIVER
VCXO
DAC
1.1MHz
HC1
ANALOG
LOOP
138KHz
SC2
ADC
ERROR
CORRECTION
13 bits
4 bits
MUX
DIGITAL
LOOP
DIGITAL
IF
DAC
MUX
12 bits
4 bits
August 1999
D99TL453
1/22
1 page  
Table 3. Pin Functions (continued)
28 AVDD4
34 AVSS4
35 AVSS5
41 AVDD5
42 AVDD6
51 AVSS6
52 AVSS2
54 AVDD2
58 AVDD1
61 AVSS1
62 DVSS2
SPARES
3 NU3
4 NU2
5 NU1
6 NU0
29 NC0
30 NC1
TX pre - drivers supply
CT filter supply
LNA supply
DAC and support circuit
XTAL oscillator supply voltage
Not used inputs
Not used inputs
Not used inputs
Not used inputs
1 LT ↔ AUT-C; NT ↔ ATU-R
Figure 3. Grounding and Decoupling Networks.
STLC60134S
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
DVSS
DVSS
DVSS
DVSS
DVSS
VRAP pin
10µF
100nF
10µF
10µF
100nF
VRAN pin
ANALOG
VDD
4.7µH
L1
10µF
100nF
AVDD (each pin must
have its own capacitor)
100nF
10µF
100nF
VREF pin
IREF pin
100nF
VCOC pin
10µF
100nF
10µF
AGND pin
D98TL356
ATU-C END: BLOCK DIAGRAM
The transformer at ATU-C side has 1:2 ratio. The
termination resistors are 12.5Ω in case of 100Ω
lines.
The hybrid bridge resistors should be < 2.5kΩ for
low-noise.
An HP filter must be used on the TX path to re-
duce DMT sidelobes and out of band noise influ-
ence on the receiver. On the RX path, a LP filter
must be used in order to reduce the echo signal
level and to avoid saturation of the input stage of
the receiver.
The POTS filter is used in both directions to re-
duce crosstalk between STLC60134S signals
and POTS speech and signalling.
5/22
5 Page 
STLC60134S
Table 15. Phase characteristics
Description
Total TX filter group delay
Total TX filter group delay distortion
Value/Unit
<50µs @ 34.5kHz < f < 138kHz
<20µs @ 34.5kHz < f < 138kHz
Note: The total ATU-R TX path (including DAC) group delay distortion is 16µs (i.e. = 15µs + 1µs of DAC)
Figure 10. SC Filter Mask for ATU-CRX and ATU-R TX
AMPLITUTDE
0dB
+/-1dB
20dB
30 D98TL363
138 250
KHz
Table 16. D/A Convertor (A current steering architecture is used).
Description
Numbers of bits:
Minimum resolution of the D/A convertors
Linearity error of the A/D convertor
Full scale input range:
Sampling rate:
Maximum group delay:
Maximum group delay distortion:
Value/Unit
12bits
11bits
<1LSB (out of 12bits)
1 Vpdif ±5%
8.832MHz (or 4.416MHz in compatible mode)
<3µs
<1µs
Linearity of ATU-C TX
Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and
each with 0.5Vpd amplitude (total ≤ 1Vpd) at the output of the pre-driver for the case of a total AGC = 0dB.
Table 17. Linearity of ATU-C TX
f1 (0.5Vpd)
f2 (0.5Vpd)
S/IM3 (AGC = 0dB)
300kHz
200kHz
59.5dB @ 100kHz
53.5dB @ 400kHz
43.5dB @ 700kHz
42.5dB @ 800kHz
500kHz
400kHz
59.5dB @ 300kHz
48.0dB @ 600kHz
700kHz
600kHz
48.0dB @ 500kHz
42.5dB @ 800kHz
11/22
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