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PDF AM486DX4 Data sheet ( Hoja de datos )
| Número de pieza | AM486DX4 | |
| Descripción | 3V / Clock-Selectable / 32-Bit Microprocessor | |
| Fabricantes | AMD | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AM486DX4 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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PRELIMINARY
Am486® DX4 3-Volt Processor
Advanced
Micro
High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor Devices
DISTINCTIVE CHARACTERISTICS
Operating voltage range 3.3 V ± 0.3 V
— 120-MHz operating frequency uses a 40-MHz
external bus
— 100-MHz operating frequency uses a 33-MHz
external bus
— Wide range of chipsets and support available
through the AMD FusionPCSM Program
High Integration On-Chip
— 8-Kbyte code and data cache
— Floating-point unit
— Paged, virtual memory management
High-Performance Design
— Frequent instructions execute in one clock
— 105.6-Million bytes/second burst bus at 33 MHz
— 128-Million bytes/second burst bus at 40 MHz
— 0.5-micron CMOS process technology
— Dynamic bus sizing for 8, 16, and 32-bit buses
Complete 32-Bit Architecture
— Address and data buses
— All registers
— 8, 16, and 32-bit data types
Multiprocessor Support
— Multiprocessor instructions
— Cache consistency protocols
— Support for second-level cache
Standard 168-Pin PGA Package
Supports Environmental Protection Agency’s
(EPA) “Energy Star” program
— Energy management capability provides excel-
lent base for energy-efficient design
— Works with a variety of energy efficient, power
managed devices
GENERAL DESCRIPTION
The Am486DX4 microprocessor is a high-performance
486 desktop solution that provides optimal price/perfor-
mance for high-end 486 power-managed systems. The
Am486DX4 CPU offers superior local bus graphics per-
formance for Microsoft® Windows®.
Using AMD’s speed-multiplying technology, the
Am486DX4 CPU and cache operate two to three times
faster than the external memory bus. It is manufactured
The Am486DX4 processor operates with a 1X clock in-
put. This 1X clock simplifies system design by reducing
the clock frequency required by external devices. The
1X clock also reduces RF emission and simplifies clock
generation. The input signal is doubled or tripled inter-
nally to achieve the maximum 2X or 3X operating fre-
quency. The phases of the core clock are controlled by
an internal Phase Lock Loop (PLL) circuit.
using AMD’s new 3.3-V CMOS process technology to
consume about 2.6 watts of power at 100 MHz or 3.2
watts at 120 MHz. This 3.3-V technology provides su-
perior solutions for low-power EPA’s Energy Star
mGreen PCs and portables.
w.datasheet4u.coThis document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
ww product without notice.
Publication#19160 Rev: D Amendment/0
Issue Date: July 1995
1 page  
PRELIMINARY
CONNECTION DIAGRAMS
Am486DX4 CPU
Top Side View
168-Pin PGA (Pin Grid Array) Package
AMD
17 16 15 14 13 12
ADS A4 A6 VSS A10 VSS
S
NC BLAST A3 VCC A8 A11
R
PCHK PLOCK BREQ A2 A7 A5
Q
VSS VCC HLDA
P
W/R M/IO LOCK
N
VSS VCC D/C
M
VSS VCC PWT
L
VSS VCC BE0
K
PCD BE1 BE2
J
VSS VCC BRDY
H
VSS VCC NC
G
BE3 RDY KEN
F
VSS VCC HOLD
E
BOFF BS8 A20M
D
BS16 RESET FLUSH FERR NC NC
C
EADS TDO NMI TMS CLKMUL NC
B
AHOLD INTR IGNNE TDI NC NC
A
11 10
VSS VSS
987 654 32 1
VSS VSS A12 VSS A14 VOLDET A23 A26 A27
VCC VCC VCC VCC A15 VCC A18 VSS VCC A25 A28
A9 A13 A16 A20 A22 A24 A21 A19 A17 VSS A31
A30 A29 D0
DP0 D1 D2
D4 VCC VSS
D7 D6 VSS
D14 VCC VSS
D16 D5 INC
DP2 D3 VSS
D12 VCC VSS
D15 D8 DP1
D10 VCC VSS
D17 D13 D9
UP NC D30 D28 D26 D27 VCC VCC CLK D18 D11
VCC NC
VCC D31 VCC D25
VSS VSS VSS D21 D19
VSS NC VSS D29 VSS D24 DP3 D23 TCK D22 D20
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Note:
NC = No connect. To guarantee functionality with future revisions, these pins must not be connected.
19160c-003
Am486DX4 Microprocessor
5
5 Page 
PRELIMINARY
AMD
PCHK
Parity Status (Active Low; Output)
Parity status is driven on the PCHK pin the clock after
RDY for read operations for data sampled at the end of
the previous clock. A parity error is indicated by PCHK
being Low. Parity status is only checked for enabled
bytes as indicated by the byte enable and bus size sig-
nals. PCHK is valid only in the clock immediately after
read data is returned to the microprocessor. At all other
times PCHK is inactive High. PCHK is never floated ex-
cept during three-state test mode (see FLUSH).
PLOCK
Pseudo-Lock (Active Low; Output)
PLOCK indicates that the current bus transaction re-
quires more than one bus cycle to complete. Examples
of such operations are floating-point long reads and
writes (64 bits), segment table descriptor reads (64 bits),
and cache line fills (128 bits). The Am486DX4 micro-
processor drives PLOCK active until the addresses for
the last bus cycle of the transaction have been driven,
regardless of whether RDY or BRDY has been returned.
Normally PLOCK and BLAST are inverse of each other.
However, during the first bus cycle of a 64-bit floating-
point write, both PLOCK and BLAST will be asserted.
PLOCK is a function of the BS8, BS16, and KEN inputs.
PLOCK should be sampled only if the clock RDY is re-
turned. PLOCK is active Low and is not driven during
bus hold.
RESET
Reset (Active High; Input)
This pin forces the Am486DX4 microprocessor to begin
execution at a known state. The microprocessor cannot
begin execution of instructions until at least 1 ms after
VCC and CLK have reached their proper DC and AC
specifications. The RESET pin should remain active
during this time to ensure proper microprocessor oper-
ation. RESET is active High. RESET is asynchronous
but must meet setup and hold times, t20 and t21, for rec-
ognition in any specific clock.
RDY
Non-Burst Ready (Active Low; Input)
This input pin indicates that the current bus cycle is com-
plete. RDY indicates that the external system has pre-
sented valid data on the data pins in response to a read,
or that the external system has accepted data from the
Am486DX4 microprocessor in response to a write. RDY
is ignored when the bus is idle and at the end of the bus
cycle’s first clock.
RDY is active during address hold. Data can be returned
to the processor while AHOLD is active.
RDY is active Low and is not provided with an internal
pull-up resistor. RDY must satisfy setup and hold times,
t16 and t17, for proper chip operation.
TCK
Test Clock (Input)
Test Clock is an input to the Am486DX4 CPU and pro-
vides the clocking function required by the JTAG bound-
ary scan feature. TCK is used to clock state information
and data into and out of the component. State select
information and data are clocked into the component on
the rising edge of TCK on TMS and TDI, respectively.
Data is clocked out of the component on the falling edge
of TCK on TDO.
TDI
Test Data Input (Input)
TDI is the serial input used to shift JTAG instructions
and data into the component. TDI is sampled on the
rising edge of TCK, during the SHIFT-IR and the
SHIFT-DR TAP controller states. During all other tap
controller states, TDI is a “don’t care.”
TDO
Test Data Output (Output)
TDO is the serial output used to shift JTAG instructions
and data out of the component. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR
Test Access Port (TAP) controller states. At all other
times, TDO is driven to the high-impedance state.
TMS
Test Mode Select (Input)
TMS is decoded by the JTAG TAP to select the operation
of the test logic. TMS is sampled on the rising edge of
TCK. To guarantee deterministic behavior of the TAP
controller, TMS is provided with an internal pull-up re-
sistor.
UP
Upgrade Present (Active Low; Input)
The Upgrade Present pin forces the Am486DX4 CPU
to three-state all its outputs and enter the power-down
mode. When the Upgrade Present pin is sampled as-
serted by the CPU in the clock before the falling edge
of RESET, the power-down mode is enabled. UP has
no effect on the power-down status except during this
edge. The CPU is also forced to three-state all of its
outputs immediately in response to this signal. The UP
signal must remain asserted in order to keep the pins
three-state. UP is active Low and is provided with an
internal pull-up resistor.
VOLDET
Voltage Detect (Active Low; Output)
The voltage detect signal allows external system logic
to distinguish between a 5-V Am486 processor and the
3.3-V Am486DX4 processor. The signal is active Low
for a 3.3-V Am486DX4 processor.
Am486DX4 Microprocessor
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AM486DX4.PDF ] | |
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