|
|
PDF AM486DX2 Data sheet ( Hoja de datos )
| Número de pieza | AM486DX2 | |
| Descripción | 3.3V / Clock-Doubled / 32-Bit Microprocessor | |
| Fabricantes | AMD | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AM486DX2 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
PRELIMINARY
Am486® DX2 3.3-Volt Processor
High-Performance, Clock-Doubled, 32-Bit Microprocessor
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
Operating voltage range 3.3 V ± 0.3 V
— 66-MHz and 80-MHz operating frequencies
— Wide range of chipsets and support available
through the AMD® FusionPCSM Program
High Integration On-Chip
— 8-Kbyte code and data cache
— Floating-point unit
— Paged, virtual memory management
High-Performance Design
— Frequent instructions execute in one clock
— 105.6-million bytes/second burst bus at 33 MHz
— 128-million bytes/second burst bus at 40 MHz
— Advanced submicron CMOS technology
— Dynamic bus sizing for 8-, 16-, and 32-bit buses
Complete 32-Bit Architecture
— Address and data buses
— All registers
— 8-, 16-, and 32-bit data types
Multiprocessor Support
— Multiprocessor instructions
— Cache consistency protocols
— Support for second-level cache
Standard 168-pin PGA Package
Environmental Protection Agency's “Energy
Star” program compliant
— Energy management capability provides an
excellent base for energy-efficient design
— Works with a variety of energy-efficient,
power-managed devices
GENERAL DESCRIPTION
The clock-doubled Am486DX2 processor is a high-per-
formance 486 desktop solution that provides optimal
price/performance for high-end 486 power-managed
systems. The Am486DX2 CPU offers superior local bus
graphics performance for Microsoft® Windows®.
The Am486DX2 processor operates with a 1x clock in-
put. This 1x clock simplifies system design by reducing
the clock frequency required by external devices. The
1x clock also reduces RF emission and simplifies clock
generation. The input signal is doubled internally to
achieve the maximum 2x operating frequency. The
phases of the core clock are controlled by an internal
Phase Lock Loop (PLL) circuit.
w.datasheet4u.comThis document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
ww product without notice.
Publication# 19200 Rev: D Amendment/0
Issue Date: August 1995
1 page  
PRELIMINARY
CONNECTION DIAGRAMS
Am486DX2 CPU
Top Side View
168-Pin PGA (Pin Grid Array) Package
AMD
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ADS A4 A6
VSS A10 VSS
VSS VSS VSS VSS A12 VSS A14 VOLDET A23 A26 A27
S
INC BLAST A3 VCC A8 A11 VCC VCC VCC VCC A15 VCC A18 VSS VCC A25 A28
R
PCHK PLOCK BREQ A2 A7 A5 A9 A13 A16 A20 A22 A24 A21 A19 A17 VSS A31
Q
VSS VCC HLDA
A30 A29 D0
P
W/R M/IO LOCK
N
VSS VCC D/C
M
VSS VCC PWT
L
VSS VCC BE0
K
PCD BE1 BE2
J
VSS VCC BRDY
H
VSS VCC INC
G
DP0 D1 D2
D4 VCC VSS
D7 D6 VSS
D14 VCC VSS
D16 D5 INC
DP2 D3 VSS
D12 VCC VSS
BE3 RDY KEN
F
VSS VCC HOLD
E
D15 D8 DP1
D10 VCC VSS
BOFF BS8 A20M
D
D17 D13 D9
BS16 RESET FLUSH FERR NC INC UP INC D30 D28 D26 D27 VCC VCC CLK D18 D11
C
EADS TDO NMI TMS CLKMUL INC VCC INC VCC D31 VCC D25 VSS VSS VSS D21 D19
B
AHOLD INTR IGNNE TDI INC INC
A
VSS INC
VSS D29 VSS D24 DP3 D23 TCK D22 D20
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Note:
NC = No Connect. To guarantee functionality with future revisions, these pins must not be connected.
INC = Internal No Connect. No special requirements.
19200C-003
Am486DX2 Microprocessor
5
5 Page 
PRELIMINARY
AMD
PLOCK
Pseudo-Lock (Active Low; Output)
PLOCK indicates that the current bus transaction re-
quires more than one bus cycle to complete. Examples
of such operations are floating-point long reads and
writes (64 bits), segment table descriptor reads (64 bits),
and cache line fills (128 bits). The Am486DX2 micro-
processor drives PLOCK active until the addresses for
the last bus cycle of the transaction have been driven,
regardless of whether RDY or BRDY has been returned.
Normally, PLOCK and BLAST are inverse of each other.
However, during the first bus cycle of a 64-bit floating-
point write, both PLOCK and BLAST will be asserted.
PLOCK is a function of the BS8, BS16, and KEN inputs.
PLOCK should be sampled only if the clock RDY is re-
turned. PLOCK is active Low and is not driven during
bus hold.
RESET
Reset (Active High; Input)
This pin forces the Am486DX2 microprocessor to begin
execution at a known state. The microprocessor cannot
begin execution of instructions until at least 1 ms after
VCC and CLK have reached proper DC and AC specifi-
cations. The RESET pin should remain active during
this time to ensure proper microprocessor operation.
RESET is active High. RESET is asynchronous but
must meet setup and hold times t20 and t21 for recogni-
tion in any specific clock.
RDY
Non-Burst Ready (Active Low; Input)
This input pin indicates that the current bus cycle is
complete. RDY indicates that the external system has
presented valid data on the data pins in response to a
read, or that the external system has accepted data from
the Am486DX2 microprocessor in response to a write.
RDY is ignored when the bus is idle and at the end of
the bus cycle’s first clock.
RDY is active during address hold. Data can be returned
to the processor while AHOLD is active.
RDY is active Low and is not provided with an internal
pull-up resistor. RDY must satisfy setup and hold times
t16 and t17 for proper chip operation.
TDI
Test Data Input (Input)
TDI is the serial input used to shift JTAG instructions
and data into the component. TDI is sampled on the
rising edge of TCK, during the SHIFT-IR and the
SHIFT-DR TAP controller states. During all other tap
controller states, TDI is a “don’t care.”
TDO
Test Data Output (Output)
TDO is the serial output used to shift JTAG instructions
and data out of the component. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR
TAP controller states. At all other times, TDO is driven
to the high impedance state.
TMS
Test Mode Select (Input)
TMS is decoded by the JTAG TAP (Test Access Port)
to select the operation of the test logic. TMS is sampled
on the rising edge of TCK. To guarantee deterministic
behavior of the TAP controller, TMS is provided with an
internal pull-up resistor.
UP
Upgrade Present (Active Low; Input)
The Upgrade Present pin forces the Am486DX2 CPU
to three-state all its outputs and enter the power-down
mode. When the Upgrade Present pin is sampled as-
serted by the CPU in the clock before the falling edge
of RESET, the power-down mode is enabled. UP has
no effect on the power-down status expect during this
edge. The CPU is also forced to three-state all of its
outputs immediately in response to this signal. The UP
signal must remain asserted in order to keep the pins
three-state. UP is active Low and is provided with an
internal pull-up resistor.
VOLDET
Voltage Detect (Output)
The voltage detect signal allows external system logic
to distinguish between a 5-V Am486 processor and the
3.3-V Am486DX2 processor. The signal is active Low
for a 3.3-V Am486DX2 processor.
TCK
Test Clock (Input)
Test Clock is an input to the Am486DX2 CPU and pro-
vides the clocking function required by the JTAG bound-
ary scan feature. TCK is used to clock state information
and data into and out of the component. State select
information and data are clocked into the component on
the rising edge of TCK on TMS and TDI, respectively.
Data is clocked out of the component on the falling edge
of TCK on TDO.
Am486DX2 Microprocessor
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AM486DX2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AM486DX | Microprocessor | AMD |
| AM486DX2 | 3.3V / Clock-Doubled / 32-Bit Microprocessor | AMD |
| AM486DX4 | 3V / Clock-Selectable / 32-Bit Microprocessor | AMD |
| AM486DX5 | Microprocessor Family | AMD |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |