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PDF STLC5445 Data sheet ( Hoja de datos )
| Número de pieza | STLC5445 | |
| Descripción | QUAD LINE FEED CONTROLLER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STLC5445
QUAD LINE FEED CONTROLLER
s BATTERY VOLTAGE UP TO 120V
s SUPPLIES POWER FOR UP TO FOUR
DIGITAL TELEPHONE LINES
s PROGRAMMABLE CURRENT LIMITING
s LONGITUDINAL CURRENT CANCELLATION
s ETSI ETR80 COMPLIANT
s OUTPUT CURRENT UP TO 140 mA
s STATUS CONDITION DETECTION FOR
EACH LINE
s AUTOMATIC THERMAL PROTECTION
s AUTO POWER ON SEQUENCE
s OUTPUT STAGE OPTIMIZED FOR MINIMAL
OUTPUT OVERVOLTAGE PROTECTION
s TWO EXTERNAL RELAY DRIVERS PER LINE
s PARALLEL OR MPI CONTROL INTERFACE
s HI-QUAD PACKAGE 64 PIN
DESCRIPTION
The QUAD LINE FEED CONTROLLER provides a
power source for up to four U line interfaces. The
power source to the device is a local battery or a cen-
tralized regulated power supply. Each powered line is
individually controlled and monitored by the device
interface.
A MPI or a simple parallel interface can be selected
HiQUAD-64
ORDERING NUMBER: STLC5445
by a pin strap.
Each line can be individually powered and monitored:
therefore overload and faults can easily be detected
and localized even in a large system. The status con-
ditions detected by the device are: Current Overload,
Thermal Overload, Open Loop. If activated (by
means of a dedicated pin strap), a self generated
power on sequence avoids the thermal over stress
when a simultaneous power on has been requested
for more than one channel. The current limiting value
can globally be programmed for the four channels by
means of an external resistor. The device has two in-
tegrated relay drivers per line to drive the test relays
of the ISDN system.
October 2002
1/23
1 page  
PIN FUNCTION (continued)
N° Pin Name
Description
45 *EREL3A Logic input pin: relay 3A output driver’s ON/OFF (high = ON)
46 *ERL3B Logic input pin: relay 3B output driver’s ON/OFF (high = ON)
47 REL3B Output of the 3B relay driver
48 NACK2 (D2) Logic pin: with PSC = 0, Line 2 status information output
with PSC = 1, Line 2 I/O tristate data bus
49 NACK3 (D3) Logic pin: with PSC = 0 line 3 status information output
with PSC = 1 line 3 I/O tristate data bus
50 *RESETN Logic input pin: reset (active low)
53
WA3
Output feeder’s switch side of line 3; negative respect toWB3
55
ILIM
Current limit programming input
56 WBP3 Internal protection diodes for line 3
57
WB3
Output feeder’s resistive side of line 3; positive respect to WA3
60
WB0
Output feeder’s resistive side of line 0; positive respect to WA0
61 WBP0 Internal protection diodes for line 0
0
WA0
Output feeder’s switch side of line 0; negative respect to WB0
26 VBAT Negative battery supply voltage. It is referred to BGND
27
58
59
19 BGND Battery ground
32
51
64
3 RGND Relay ground
35
62
* Internal pull down to ground
STLC5445
5/23
5 Page 
Figure 3. Microprocessor WRITE timing
STLC5445
ALE
AO
CS
RD
DATA
tAHAL
tADAL
tADAZ
tCLRL (Note 1)
tADDA
tAZRL
tRLRH
tRLDA
tRHCH (Note 2)
tRHDZ
Read Data
tRHRL
D94TL108A
Notes: 1. If tCLWL is negative tWLWH is measured from CS_ rather than fromWR_.
2. If tWHCH is negative, tWHWL, tWLWH, tDAWH and tWHDZ are measured from CS_ rather than fromWR_.
The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1ms for both mask and enabl e operations.
Figure 4. Microprocessor READ timing
ALE
AO
CS
tAHAL
tADAL
tADAZ
tWHCH (Note 2)
WR
DATA
INT
tCLWL (Note 1)
tAZWL
tWLWH
tDAWH
tWHDZ
Write Data
(Note 3)
tWHWL
D94TL109A
Notes: 1. If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS_ rather than RD_.
2. If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS_ rather than RD_.
When a read from the LER immediately follows a write to the LER a minimum of 1ms is required between these operations
11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet STLC5445.PDF ] | |
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