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PDF MC145191 Data sheet ( Hoja de datos )
| Número de pieza | MC145191 | |
| Descripción | 1.1 GHz PLL Frequency Synthesizers | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145190/D
1.1 GHz PLL Frequency
Synthesizers
Include On–Board 64/65 Prescalers
MC145190
MC145191
The MC145190 and MC145191 are single–package synthesizers with serial
interfaces capable of direct usage up to 1.1 GHz. A special architecture makes
these PLLs very easy to program because a byte–oriented format is utilized.
Due to the patented BitGrabber™ registers, no address/steering bits are
required for random access of the three registers. Thus, tuning can be
accomplished via a 3–byte serial transfer to the 24–bit A register. The interface
is both SPI and MICROWIRE™ compatible.
Each device features a single–ended current source/sink phase detector
output and a double–ended phase detector output. Both phase detectors have
linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
The MC145190 features logic–level converters and high–voltage phase/
frequency detectors; the detector supply may range up to 9.5 V. The
MC145191 has lower–voltage phase/frequency detectors optimized for
single–supply systems of 5 V ± 10%.
Each part includes a differential RF input which may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the parts to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
• Maximum Operating Frequency: 1100 MHz @ Vin = 200 mV p–p
• Operating Supply Current: 7 mA Nominal
• Operating Supply Voltage Range (VDD and VCC Pins): 4.5 to 5.5 V
• Operating Supply Voltage Range of Phase Detectors (VPD Pin) —
MC145190: 8.0 to 9.5 V
MC145191: 4.5 to 5.5 V
• Current Source/Sink Phase Detector OUTPUT Capability: 2 mA Maximum
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
• Operating Temperature Range: – 40 to + 85°C
• R Counter Division Range: (1 and) 5 to 8191
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 4 Mbps
• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
• Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
OUTPUT B: Open–Drain
• Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
• Evaluation Kit Available (Part Numbers MC145190EVK and MC145191EVK)
• See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
20
1
F SUFFIX
SOG PACKAGE
CASE 751J
20
1
DT SUFFIX
TSSOP
CASE 948D
ORDERING INFORMATION
MC145190F SOG Package
MC145191F SOG Package
MC145190DT TSSOP
MC145191DT TSSOP
PIN ASSIGNMENT
REFout
LD
φR
φV
VPD
PDout
GND
Rx
TEST 1
fin
1
2
3
4
5
6
7
8
9
10
20 REFin
19 Din
18 CLK
17 ENB
16 OUTPUT A
15 OUTPUT B
14 VDD
13 TEST 2
12 VCC
11 fin
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 5
1/98 TN98012300
©MOMoTtoOroRla,OInLc.A1998
MC145190•MC145191
1
1 page  
SWITCHING WAVEFORMS
tf tr
90%
CLK 50%
10%
OUTPUT A
(DATA OUT)
90%
50%
10%
tw
1/fclk
tPLH
tTLH
tw
tPHL
tTHL
Figure 1.
VDD ENB 50%
GND
tPLH tPHL
OUTPUT A
50%
tPLZ tPZL
OUTPUT B
10%
Figure 2.
VDD
GND
50%
VALID
Din 50%
tsu th
CLK 50%
Figure 3.
VDD ENB 50%
tw
GND
tsu th
VDD
GND CLK 50%
FIRST
CLK
LAST
CLK
tw
trec
VDD
GND
VDD
GND
Figure 4.
TEST POINT
DEVICE
UNDER
TEST
CL*
*Includes all probe and fixture capacitance.
Figure 5. Test Circuit
DEVICE
UNDER
TEST
V+
TEST POINT
7.5 kΩ
CL*
*Includes all probe and fixture capacitance.
Figure 6. Test Circuit
MOTOROLA
MC145190•MC145191
5
5 Page 
floating state when the device is put into standby (STBY bit
C4 = high).
The PDout circuit is powered by VPD. The phase detec-
tor gain is controllable by bits C3, C2, and C1: gain (in
amps per radian) = PDout current divided by 2π.
φR and φV (Pins 3 and 4)
Double–Ended Phase/Frequency Detector Outputs
These outputs can be combined externally to generate
a loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized
by a linear transfer function. The operation of the phase/
frequency detector is described below and is shown in
Figure 18.
POL bit (C7) in the C register = low (see Figure 15)
Frequency of fV > fR or Phase of fV Leading fR: φV = nega-
tive pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV = essen-
tially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essen-
tially high, except for a small minimum time period when
both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR = nega-
tive pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR = essen-
tially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essen-
tially high, except for a small minimum time period when
both pulse low in phase
These outputs can be enabled, disabled, and inter-
changed via C register bits C6 or C4. This is a patented fea-
ture. Note that when disabled or in standby, φR and φV are
forced to their rest condition (high state).
The φR and φV output signal swing is approximately from
GND to VPD.
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when
fV and fR are out of phase or different frequencies. LD is
the logical ANDing of φR and φV (see Figure 18).
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip initializa-
tion circuitry disables LD to a static low logic level to prevent
a false “lock” signal. If unused, LD should be disabled and
left open.
The LD output signal swing is approximately from GND to
VDD.
Rx
External Resistor (Pin 8)
A resistor tied between this pin and GND, in conjunction
with bits in the C register, determines the amount of current
that the PDout pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PDout;
see Tables 2 and 3 for other values of current. To achieve a
maximum current of 2 mA, the resistor should be about
47 kΩ when VPD is 9 V or about 18 kΩ when VPD is 5.0 V.
See Figure 14 if lower maximum current values are desired.
When the φR and φV outputs are used, the Rx pin may be
floated.
TEST POINT PINS
TEST 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
CAUTION
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
TEST 2
Prescaler Output (Pin 13)
This pin may be used to access to the on–board 64/65
prescaler output.
CAUTION
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
POWER SUPPLY PINS
VDD
Positive Power Supply (Pin 14)
This pin supplies power to the main CMOS digital por-
tion of the device. The voltage range is + 4.5 to + 5.5 V
with respect to the GND pin.
For optimum performance, VDD should be bypassed to
GND using a low–inductance capacitor mounted very
close to these pins. Lead lengths on the capacitor should
be minimized.
VCC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65 pre-
scaler. The voltage range is + 4.5 to + 5.5 V with respect to
the GND pin. In the standby mode, the VCC pin still draws a
few milliamps from the power supply. This current drain can
be eliminated with the use of transistor Q1 as shown in
Figure 22.
For optimum performance, VCC should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin must be no less than
the potential applied to the VDD pin. The maximum voltage
can be + 9.5 V with respect to the GND pin for the MC145190
and + 5.5 V for the MC145191.
For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND
Ground (Pin 7)
Common ground.
MOTOROLA
MC145190•MC145191
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MC145191.PDF ] | |
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