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PDF MC145192 Data sheet ( Hoja de datos )
| Número de pieza | MC145192 | |
| Descripción | Low-Voltage 1.1 GHz PLL Frequency Synthesizer | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145192/D
Low-Voltage 1.1 GHz
MC145192
PLL Frequency Synthesizer
Includes On–Board 64/65 Prescaler
The MC145192 is a low–voltage single–package synthesizer with serial
interface capable of direct usage up to 1.1 GHz. A special architecture makes
this PLL very easy to program because a byte–oriented format is utilized. Due
to the patented BitGrabber™ registers, no address/steering bits are required for
20
1
F SUFFIX
SOG PACKAGE
CASE 751J
random access of the three registers. Thus, tuning can be accomplished via a
3–byte serial transfer to the 24–bit A register. The interface is both SPI and
MICROWIRE™ compatible.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
20
1
DT SUFFIX
TSSOP
CASE 948D
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
The MC145192 phase/frequency detector B φR and φV outputs can be
powered from 2.7 to 5.5 V. This is optimized for 3.0 V systems. The
ORDERING INFORMATION
MC145192F SOG Package
MC145192DT TSSOP
phase/frequency detector A PDout output must be powered from 4.5 to 5.5 V,
and is optimized for a 5 volt supply.
This part includes a differential RF input which may be operated in a
PIN ASSIGNMENT
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
REFout
LD
φR
1
2
3
20 REFin
19 DATA IN
18 CLOCK
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
φV 4
VPD 5
PDout 6
17 ENABLE
16 OUTPUT A
15 OUTPUT B
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
GND 7
Rx 8
14 VDD
13 TEST 2
the three counters (R, A, and N) simultaneously.
TEST 1 9
12 VCC
• Maximum Operating Frequency: 1100 MHz @ Vin = 200 mV p–p
• Operating Supply Current: 6 mA Nominal at 2.7 V
• Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.0 V
• Operating Supply Voltage Range of Phase Frequency Detector A
fin 10
11 fin
(VPD Pin) = 4.5 to 5.5 V
• Operating Supply Voltage Range of Phase Detector B (VPD Pin) = 2.7 to 5.5 V
• Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via Serial Port
• Operating Temperature Range: – 40° to 85°C
• R Counter Division Range: (1 and) 5 to 8191
• N Counter Division Range: 5 to 4095
• A Counter Division Range: 0 to 63
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 2 Megabits per Second
• Output A Pin, When Configured as Data Out, Permits Cascading of Devices
• Two General–Purpose Digital Outputs — Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
• Power–Saving Standby Feature with Patented Orderly Recovery for Minimizing Lock Times,
Standby Current: 30 µA
• Evaluation Kit Available (Part Number MC145192EVK)
• See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 3
1/98 TN98012200
©MOMoTtoOroRla,OInLc.A1998
MC145192
1
1 page  
tf tr
90%
CLOCK 50%
10%
OUTPUT A
(DATA OUT)
90%
50%
10%
tw
1/fclk
tPLH
tTLH
tw
tPHL
tTHL
Figure 1.
SWITCHING WAVEFORMS
VDD
ENABLE
GND
OUTPUT A
OUTPUT B
50%
tPLH tPHL
50%
tPLZ
tPZL
10%
Figure 2.
VDD
GND
50%
DATA IN
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VDD
ENABLE
50%
GND
tw
tsu
VDD
th
GND CLOCK
50%
FIRST
CLOCK
LAST
CLOCK
Figure 4.
tw
trec
VDD
GND
VDD
GND
TEST POINT
DEVICE
UNDER
TEST
CL*
* Includes all probe and fixture capacitance.
Figure 5. Test Circuit
DEVICE
UNDER
TEST
+VPD
TEST POINT
7.5 k
CL*
* Includes all probe and fixture capacitance.
Figure 6. Test Circuit
MOTOROLA
MC145192
5
5 Page 
VPD (Pin 5)
Positive Supply Potential. This pin supplies power to both
phase/frequency detectors A and B. The voltage applied on
this pin must be ≥ VDD but not more than 5.5 V. The voltage
range for VPD is 4.5 to 5.5 V with respect to the GND pin
when using PDOUT and 2.7 to 5.5 V when using φR, φV out-
puts.
For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND (Pin 7)
Common ground.
100
90
PDout CURRENT SET TO 100%;
80 PDout VOLTAGE IS FORCED TO ONE–HALF OF VPD.
70
60
50
40
30
20 VPD = 5.5 V
VPD = 5.0 V
10 VPD = 4.5 V
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3
Iout, SOURCE CURRENT (mA)
Nominal MC145192 PDout Source Current vs Rx Resistance
NOTE: The MC145192 is optimized for Rx values in the 18 kΩ to 40 kΩ range. For example, to achieve 0.3 mA of output current,
it is preferable to use a 30–kΩ resistor for Rx and bit settings for 25% (as shown in Table 3).
Figure 14.
MOTOROLA
MC145192
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MC145192.PDF ] | |
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