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PDF CS4341 Data sheet ( Hoja de datos )
| Número de pieza | CS4341 | |
| Descripción | 24-Bit / 96 kHz Stereo DAC with Volume Control | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4341
24-Bit, 96 kHz Stereo DAC with Volume Control
Features
l Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
l ATAPI Mixing
l 101 dB Dynamic Range
l 89 dBFS THD+N
l Low Clock Jitter Sensitivity
l +3 V to +5 V Power Supply
l Filtered Line Level Outputs
l On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l Digital Volume Control with Soft Ramp
– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
l 30 mW with 3 V supply
I
Description
The CS4341 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS4341 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power and oper-
ates over a wide power supply range. These features are
ideal for DVD, A/V receiver and set-top box systems.
ORDERING INFORMATION
CS4341-KS
16-pin SOIC, -10 to 70 °C
CDB4341
Evaluation Board
SCL/CCLK SDA/CDIN AD0/CS
MUTEC
RST
SCLK
LRCK
SDATA
Control Port
Interpolation Filter
Interpolation Filter
External
Mute Control
Volume Control
∆Σ DAC
Analog Filter
AOUTA
Mixer
Volume Control
∆Σ DAC
Analog Filter
AOUTB
÷2
MCLK
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
AUG ‘99
DS298PP2
1
1 page  
CS4341
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 °C; Logic "1" = VA = 5 V; Logic "0" = AGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz,
SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load RL = 10 kΩ,
CL = 10 pF (see Figure 17)),
Base-rate Mode
High-Rate Mode
Parameter
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance for VA = 5 V
Specified Temperature Range
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
TA
-10 -
92 97
96 101
- 95
- 99
70 -10
-
- 91
96
- 95 100
--
94
--
98
70 °C
- dB
- dB
- dB
- dB
Total Harmonic Distortion + Noise (Note 1) THD+N
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-89 -84 -
-77 -72 -
-37 -32 -
-88 - -
-75 - -
-35 - -
-89 -84 dB
-74 -69 dB
-36 -31 dB
-89 - dB
-73 - dB
-34 - dB
Interchannel Isolation
(1 kHz)
- 100 - - 100 - dB
Dynamic Performance for VA = 3 V
Specified Temperature Range
TA -10
-
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
99 94
A-Weighted
102 97
16-Bit unweighted
- 93
A-Weighted
- 96
70 -10
-
- 97
- 101
--
--
92
96
91
96
70 °C
- dB
- dB
- dB
- dB
Total Harmonic Distortion + Noise (Note 1) THD+N
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-94 -89 -
-74 -69 -
-34 -29 -
-93 - -
-73 - -
-33 - -
-92 -87 dB
-76 -71 dB
-32 -27 dB
-91 - dB
-71 - dB
-31 - dB
Interchannel Isolation
(1 kHz)
- 100 - - 100 - dB
Notes: 1. One-half LSB of triangular PDF dither is added to data.
DS298PP2
5
5 Page 
CS4341
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)
SPI Mode
Parameter
Symbol
Min
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 12)
(Note 13)
(Note 14)
(Note 14)
fsclk
tsrs
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
tr2
tf2
-
500
500
1.0
20
66
66
40
15
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For FSCK < 1 MHz
RST
t srs
CS
CCLK
CDIN
t spi t css
t scl t sch
t r2 t f2
t dsu t dh
Figure 5. SPI Control Port Timing
t csh
DS298PP2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4341.PDF ] | |
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