|
|
PDF CS4341A Data sheet ( Hoja de datos )
| Número de pieza | CS4341A | |
| Descripción | 24-Bit / 192 kHz Stereo DAC with Volume Control | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CS4341A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CS4341A
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
z 101 dB Dynamic Range
z -91 dB THD+N
z +3.3 V or +5 V Power Supply
z 50 mW with 3.3 V supply
z Low Clock Jitter Sensitivity
z Filtered Line-level Outputs
z On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
z ATAPI Mixing
z Digital Volume Control with Soft Ramp
– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
z Up to 200-kHz Sample Rates
z Automatic Mode Detection for Sample Rates
between 4 and 200 kHz
z Pin Compatible with the CS4341
Description
The CS4341A is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS4341A accepts data at all standard audio sample
rates up to 192 kHz, consumes very little power, oper-
ates over a wide power supply range and is pin
compatible with the CS4341, as described in section 3.1.
These features are ideal for DVD audio players.
ORDERING INFORMATION
CS4341A-KS
16-pin SOIC, -10 to 70 °C
CS4341A-KSZ, Lead Free 16-pin SOIC, -10 to 70 °C
CDB4341A
Evaluation Board
RST
SCLK
LRCK
SDIN
SCL/CCLK SDA/CDIN AD0/CS
MUTEC
Control Port
Interface
External
Mute Control
Interpolation Filter
Volume Control
∆Σ DAC
Analog Filter
AO UTA
Mixer
Interpolation Filter
Volume Control
∆Σ DAC
Analog Filter
AO UTB
÷2
MCLK
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
JUL ‘04
DS582F2
1
1 page  
1. PIN DESCRIPTION
RST 1 16 MUTEC
SDIN 2 15 AOUTA
SCLK 3 14 VA
LRCK 4 13 AGND
MCLK 5 12 AOUTB
SCL/CCLK 6 11 REF_GND
SDA/CDIN 7 10 VQ
AD0/CS 8
9 FILT+
CS4341A
Pin Name
RST
SDIN
SCLK
LRCK
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
FILT+
VQ
REF_GND
AOUTR
AOUTL
AGND
VA
MUTEC
# Pin Description
1 Reset (Input) - Powers down device when enabled.
2 Serial Audio Data (Input) - Input for two’s complement serial audio data.
3 Serial Clock (Input) -Serial clock for the serial audio interface.
4 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
6 Serial Control Port Clock (Input) - Serial clock for the control port interface.
7 Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Input for SPI data.
8 Address Bit / Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select
the chip in SPI mode.
9 Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-
cuits.
10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
11 Reference Ground (Input) - Ground reference for the internal sampling circuits.
12 Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac-
15 teristics table.
13 Analog Ground (Input) - Ground reference.
14 Power (Input) - Positive power for the analog, digital, control port interface, and serial audio
interface sections.
16 Mute Control (Output) - Control signal for optional mute circuit.
DS582F2
5
5 Page 
CS4341A
3.9 Control Port Interface
The control port is used to load all the internal register settings (see section 5). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I2C or SPI.
Notes: MCLK must be applied during all I2C communication.
3.9.1 Rise Time for Control Port Clock
When excess capacitive loading is present on the I2C clock line, pin 6 (SCL/CCLK) may not have
sufficient hysteresis to meet the standard I2C rise time specification. This prevents the use of com-
mon I2C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt
Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341A. This will not
affect the operation of the I2C bus as pin 6 is an input only.
VA
SCL
Pin 6
Figure 6. I2C Buffer Example
3.9.2 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes
or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written,
allowing block reads or writes of successive registers.
DS582F2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4341A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CS4341 | 24-Bit / 96 kHz Stereo DAC with Volume Control | Cirrus Logic |
| CS4341A | 24-Bit / 192 kHz Stereo DAC with Volume Control | Cirrus Logic |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |