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PDF MC145193 Data sheet ( Hoja de datos )
| Número de pieza | MC145193 | |
| Descripción | 1.1 GHZ PLL FREQUENCY SYNTHESIZER | |
| Fabricantes | Motorola Semiconductors | |
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Order this document by MC145193/D
1.1 GHz PLL Frequency
Synthesizer
MC145193
The MC145193 is recommended for new designs and offers reduced
power consumption. The counters are programmed via a synchronous serial
port which is SPI compatible. The serial port is byte-oriented to facilitate
control via an MCU. Due to the innovative BitGrabber Plus™ registers, the
MC145193 may be cascaded with other peripherals featuring BitGrabber
Plus without requiring leading dummy bits or address bits in the serial data
stream. In addition, BitGrabber Plus peripherals may be cascaded with
existing BitGrabber™ peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor
tied from the Rx pin to ground. This current can be varied via the serial port.
Slew–rate control is provided by a special driver designed for the REFout
pin. This minimizes interference caused by REFout.
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external
crystal and a programmable reference output. The R, A, and N counters are
fully programmable. The C register (configuration register) allows the part to
be configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from
being loaded into the counters, on–board circuitry synchronizes the update
of the A register if the A or N counters are loading. Similarly, an update of the
R register is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented
to the three counters (R, A, and N) simultaneously.
• Maximum Operating Frequency: 1100 MHz @ – 10 dBm
• Operating Supply Current: 3 mA Nominal at 3.0 V
• Operating Supply Voltage Range (VDD, VCC, VPD Pins): 2.7 to 5.5 V
• Current Source/Sink Phase Detector Output:
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
• R Counter Division Range: 1 and 5 to 8191
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 4 Mbps
• Output A Pin, When Configured as Data Out, Permits Cascading of
Devices
• Two General–Purpose Digital Outputs:
Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
• Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
• See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for
Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
PLL FREQUENCY
SYNTHESIZER
SEMICONDUCTOR
TECHNICAL DATA
20
1
F SUFFIX
PLASTIC PACKAGE
CASE 751J
(SO–20)
PIN CONNECTIONS
REFout 1
LD 2
φR
φV
VPD
PDout
Gnd
3
4
5
6
7
Rx 8
Test 1 9
fin 10
(Top View)
20 REFin
19 Din
18 CLK
17 ENB
16 Output A
15 Output B
14 VDD
13 Test 2
12 VCC
11 fin
EVALUATION KIT
The MC145193EVK, which contains
hardware and software, is available.
ORDERING INFORMATION
Device
Operating
Temperature Range Package
MC145193F TA = –40 to 85°C
SO–20
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
© Motorola, Inc. 2000
Rev 1
1
1 page  
MC145193
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)
Parameter
Figure
No.
Serial Data Clock Frequency (Note: Refer to Clock tw below)
Maximum Propagation Delay, CLK to Output A (Selected as Data Out)
1
1, 5
Maximum Propagation Delay, ENB to Output A (Selected as Port)
2, 5
Maximum Propagation Delay, ENB to Output B
2, 6
Maximum Output Transition Time, Output A and Output B; tTHLonly, on Output B
Maximum Input Capacitance – Din, ENB, CLK
1, 5, 6
Guaranteed
Symbol
Limit
fclk
tPLH, tPHL
tPLH, tPHL
tPZL, tPLZ
tTLH, tTHL
Cin
dc to 4.0
100
150
150
50
10
Unit
MHz
ns
ns
ns
ns
pF
TIMING REQUIREMENTS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)
Parameter
Figure
No.
Minimum Setup and Hold Times, Din vs CLK
Minimum Setup, Hold and Recovery Times, ENB vs CLK
3
4
Minimum Pulse Width, ENB
4
Minimum Pulse Width, CLK
1
Maximum Input Rise and Fall Times, CLK
1
NOTE: The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
Symbol
tsu, th
tsu, th, trec
tw
tw
tr, tf
Guaranteed
Limit
Unit
50 ns
100 ns
[Note]
cycles
125 ns
100 µs
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
5
5 Page 
MC145193
PDout
Single–Ended Phase/Frequency Detector Output (Pin 6)
This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a
linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR:
current–sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR:
current–sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR:
current–sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR:
current–sinking pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the
high–impedance state by utilization of the disable feature in
the C register (bit C6). This is a patented feature. Similarly,
PDout is forced to the high–impedance state when the device
is put into standby (STBY bit C4 = high).
The PDout circuit is powered by VPD. The phase detector
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PDout current divided by 2π.
φR and φV (Pins 3 and 4)
Double–Ended Phase/Frequency Detector Outputs
feature. Note that when disabled or in standby, φR and φV are
forced to their rest condition (high state).
The φR and φV output signal swing is approximately from
Gnd to VPD.
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when fV
and fR are out of phase or different frequencies. LD is the
logical ANDing of φR and φV (see Figure 17).
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip
initialization circuitry disables LD to a static low logic level to
prevent a false “lock” signal. If unused, LD should be disabled
and left open.
The LD output signal swing is approximately from Gnd to
VDD.
Rx
External Resistor (Pin 8)
A resistor tied between this pin and Gnd, in conjunction
with bits in the C register, determines the amount of current
that the PDout pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PDout;
see Tables 4 and 5 for other current values. The
recommended value for Rx is 3.9 kΩ (preliminary) . A value of
3.9 kΩ provides current at the PDout pin of approximately 1
mA @ VDD = 3 V and approximately 1.7 mA @ VDD = 5 V in
the 100% current mode. Note that VDD, not VPD, is a factor in
determining the current.
When the φR and φV outputs are used, the Rx pin may be
floated.
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized by
a linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: φV =
negative pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV =
essentially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR =
negative pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR =
essentially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and
interchanged via C register bits C6 or C4. This is a patented
Table 4. PDout Current*, C1 = Low with
Output A not Selected as “Port”;
Also, Default Mode When Output A
Selected as “Port”
Bit C3
Bit C2
PDout Current*
0 0 70%
0 1 80%
1 0 90%
1 1 100%
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
Table 5. PDout Current*, C1 = High with
Output A not Selected as “Port”
Bit C3
0
0
1
1
Bit C2
0
1
0
1
PDout Current*
25%
50%
75%
100%
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MC145193.PDF ] | |
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