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PDF SP6134 Data sheet ( Hoja de datos )
| Número de pieza | SP6134 | |
| Descripción | Dual Supply Synchronous Buck Controller | |
| Fabricantes | Sipex | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SP6134 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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® SP6134
Dual Supply Synchronous Buck Controller
FEATURES
■ 3V to 12V Step Down Achieved Using Dual Input
■ Small 10-Pin MSOP Package
■ 2A to 15A Ouput Capability
■ Highly Integrated Design, Minimal Components
■ UVLO Detects Both VCC and VIN
■ Short Circuit Protection with Auto-Restart
■ On-Board 1.5Ω sink (2Ω source) NFET Drivers
■ Programmable Soft Start
■ Fast Transient Response
■ High Efficiency: Greater than 94% Possible
■ A Synchronous Start-Up into a Pre-Charged Output
APPLICATIONS
■ 12V DPA
■ Communications Systems
■ Graphics Cards
VCC 1
GL 2
GND 3
VFB 4
COMP 5
SP6134
10 Pin MSOP
10 BST
9 GH
8 SWN
7 SS
6 UVIN
Now Available in Lead Free Packaging
DESCRIPTION
The SP6134 is a synchronous step-down switching regulator controller optimized for high efficiency. The part is
designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower VCC
voltage minimizes power dissipation in the part. The SP6134 is designed to drive a pair of external NFETs using a fixed
600kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown and output
short circuit protection. The SP6134 is available in the cost and space saving 10-pin MSOP.
TYPICAL APPLICATION CIRCUIT
VCC = 5V @ 30mA
RLF
3.0,5%
R3
221k, 1%
UVIN
R4
100k, 1%
DBST
MBR0530
CVCC
10µF
6.3V
GND 3
0.8V
CVCC
Ceramic
8050
X5R
CF1
100pF
U1
1 VCC
BST 10
2
SP6134
GL GH
9
3 GND
SWN 8
4 VFB
SS 7
5 COMP UVIN 6
CZ2 RZ2
820pF 40.2k, 1%
CP1
56pF
fs=600Khz
8765
QT FDS6676S
4 14.5A, 6mΩ
123
CBST
1µF
R5
Bead
8765
QB
4
SS 1 2 3
FDS6676S
CSS 14.5A, 6.0mΩ
47nF
VOUT=(R1/R2 +1)VFB
C1
22µF
16V
C2
22µF
16V
C1, C2
Ceramic
1210
X5R
VIN
3.5V - 15V
GND
C3
47µF
6.3V
C4
47µF
6.3V
RZ3
4.64k, 1%
CZ3
220pF
VOUT≤VIN
0.8V - 3.3V
0 - 10 A
R1
68.1k, 1%
GND2
C3, C4
Ceramic
1210
X5R
R2
21.5k, 1%
Date: 5/25/04
SP6134 Dual Supply, Synchronous Buck Controller
1
© Copyright 2004 Sipex Corporation
1 page  
FUNCTIONAL DIAGRAM
5 COMP
100% Protection Logic
VCC
PWM LOOP
PULSES CLR
COUNT 20
CLOCK
CLK
FAULT
VFB
VCC
Gm ERROR AMPLIFIER
VFBINT
VCC
Gm
VPOS
FAULT
10 µA
SS 7
SOFTSTART INPUT
POS REF
FAULT
FAULT
RESET
DOMINANT
R
Q
S
QPWM
RAMP = 1.1V
0.4 V
600 kHZ
CLK
CLOCK PULSE GENERATOR
VCC 1
REFERENCE
CORE
0.8V
REF OK
1.7 V
SS
1.7 V
ASYNC. STARTUP
COMPARATOR
SYNCHRONOUS
DRIVER
GL HOLD OFF
10 BST
9 GH
8 SWN
2 GL
3 GND
145 ˚C ON
135 ˚C OFF
THERMAL
SHUTDOWN
VPOS
VFBINT
0.25 V
+-
SHORT CIRCUIT
DETECTION
+
-
SET
DOMINANT
S
Q
R
HICCUP FAULT
REF OK
VCC
+
4.25 V ON
4.05 V OFF -
VCC UVLO
POWER FAULT
FAULT
+
2.50 VON
2.20 V OFF
-
VIN UVLO
CLK
COUNTER 200ms Delay
6
UVIN
CLR
REF OK
THERMAL AND SHORT CIRCUIT PROTECTION
UVLO COMPARATORS
THEORY OF OPERATION
General Overview
The SP6134 is a fixed frequency, voltage mode,
synchronous PWM controller optimized for high
efficiency. The part has been designed to be
especially attractive for split plane applications
utilizing 5V to power the controller and 3V to
12V for step down conversion.
The heart of the SP6134 is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. A precision 0.8V reference present on
the positive terminal of the error amplifier per-
mits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp and PWM
control logic are governed by the internal oscil-
lator that accurately sets the PWM frequency to
600kHz.
The SP6134 contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during start up to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The SP6134 also contains a number of valuable
protection features. A programmable input (VIN)
UVLO allows a user to set the exact value at
which the conversion voltage is at a safe point to
begin down conversion, and an internal VCC
UVLO ensures that the controller itself has
enough voltage to properly operate. Other pro-
Date: 5/25/04
SP6134 Dual Supply, Synchronous Buck Controller
5
© Copyright 2004 Sipex Corporation
5 Page 
APPLICATIONS INFORMATION: Continued
thermal improvement can be achieved in the maxi-
mum power dissipation through the proper design
of copper mounting pads on the circuit board. For
example, in a SO-8 package, placing two 0.04
square inches copper pad directly under the pack-
age, without occupying additional board space,
can increase the maximum power from approxi-
mately 1 to 1.2W. For DPAK package, enlarging
the tap mounting pad to 1 square inches reduces the
RΘJA from 96°C/W to 40°C/W.
Schottky Diode Selection
When paralleled with the bottom MOSFET, an
optional Schottky diode can improve efficiency
and reduce noises. Without this Schottky diode,
the body diode of the bottom MOSFET con-
ducts the current during the non-overlap time
when both MOSFETs are turned off. Unfortu-
nately, the body diode has high forward voltage
and reverse recovery problem. The reverse re-
covery of the body diode causes additional
switching noises when the diode turns off. The
Schottky diode alleviates these noises and addi-
tionally improves efficiency thanks to its low
forward voltage. The reverse voltage across the
diode is equal to input voltage, and the diode
must be able to handle the peak current equal to
the maximum load current.
The power dissipation of the Schottky diode is
determined by
PDIODE = 2VFIOUTTNOLFS
where
TNOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross-
over at the selected frequency FCO, the gain of
the error amplifier has to compensate for the
attenuation caused by the rest of the loop at this
frequency.
+VREF
(Volts) _
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
(SRz2Cz2+1)(SR1Cz3+1)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
PWM Stage
GPWM Gain
Block
VIN
VRAMP_PP
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
VFBK
(Volts)
R2 or
(R1 + R2)
VREF
VOUT
SP6134 Voltage Mode Control Loop with Loop Dynamic
Output Stage
GOUT (s) Gain
Block
(SRESRCOUT+ 1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
VOUT
(Volts)
Date: 5/25/04
SP6134 Dual Supply, Synchronous Buck Controller
11
© Copyright 2004 Sipex Corporation
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SP6134.PDF ] | |
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