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PDF MMDF3N03HD Data sheet ( Hoja de datos )
| Número de pieza | MMDF3N03HD | |
| Descripción | Power MOSFET 3 Amps / 30 Volts | |
| Fabricantes | ON | |
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MMDF3N03HD
Preferred Device
Power MOSFET
3 Amps, 30 Volts
N–Channel SO–8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• Logic Level Gate Drive – Can Be Driven by Logic ICs
• Miniature SO–8 Surface Mount Package – Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage – Continuous
Drain Current – Continuous @ TA = 25°C
Drain Current – Continuous @ TA = 100°C
Drain Current – Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C
(Note 1.)
VDSS
VDGR
VGS
ID
ID
IDM
PD
30 Vdc
30 Vdc
± 20 Vdc
4.1 Adc
3.0
40 Apk
2.0 Watts
Operating and Storage Temperature Range TJ, Tstg – 55 to
150
°C
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak
IL = 9.0 Apk, L = 8.0 mH, RG = 25 Ω)
Thermal Resistance – Junction to Ambient
(Note 1.)
EAS
324 mJ
RθJA
62.5 °C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
260 °C
1. When mounted on 2″ square FR–4 board (1″ square 2 oz. Cu 0.06″ thick
single sided) with one die operating, 10s max.
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3 AMPERES
30 VOLTS
RDS(on) = 70 mW
N–Channel
D
G
S
MARKING
DIAGRAM
8
SO–8, Dual
CASE 751
STYLE 11
D3N03
LYWW
1
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
Source–1
Gate–1
Source–2
Gate–2
18
27
36
45
Top View
Drain–1
Drain–1
Drain–2
Drain–2
ORDERING INFORMATION
Device
Package
Shipping
MMDF3N03HDR2 SO–8 2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2000
November, 2000 – Rev. 7
1
Publication Order Number:
MMDF3N03HD/D
1 page  
MMDF3N03HD
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
t, TIME
Figure 7. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 µs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non–linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 9). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
1200 VDS = 0 V VGS = 0 V
Ciss
1000
800
TJ = 25°C
12
9
VDS
QT
VGS
24
18
600 Crss
400
Ciss
200 Coss
Crss
010 5
0
5 10 15 20 25 30
VGS VDS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 8. Capacitance Variation
6
Q1
Q2
12
3
Q3
0
02
ID = 3 A
TJ = 25°C
4 6 8 10
Qg, TOTAL GATE CHARGE (nC)
6
0
12
Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
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5
5 Page 
Notes
MMDF3N03HD
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11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MMDF3N03HD.PDF ] | |
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