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PDF MMDF3N03HD Data sheet ( Hoja de datos )
| Número de pieza | MMDF3N03HD | |
| Descripción | DUAL TMOS POWER MOSFET 4.1 AMPERES 30 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF3N03HD/D
™Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Dual N-Channel
Field Effect Transistors
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
G
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided
MMDF3N03HD
Motorola Preferred Device
DUAL TMOS
POWER MOSFET
4.1 AMPERES
30 VOLTS
RDS(on) = 0.070 OHM
™
D
CASE 751–05, Style 11
SO–8
S
Source–1
Gate–1
Source–2
Gate–2
18
27
36
45
Top View
Drain–1
Drain–1
Drain–2
Drain–2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
Value
30
30
± 20
4.1
3.0
40
2.0
– 55 to 150
324
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
°C
mJ
RθJA
TL
62.5 °C/W
260 °C
DEVICE MARKING
D3N03
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF3N03HDR2
13″
12 mm embossed tape
2500 units
(1) When mounted on 2” square FR–4 board (1” square 2 oz. Cu 0.06” thick single sided) with one die operating, 10s max.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 6
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1
1 page  
MMDF3N03HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
1200 VDS = 0 V VGS = 0 V
Ciss
1000
TJ = 25°C
800
600 Crss
400
Ciss
200 Coss
Crss
0
10 5
0
5 10 15 20 25 30
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Capacitance Variation
1000
VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25°C
100
td(off)
tr
10
tf
td(on)
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
12
9
6
Q1
VDS
Q2
QT
VGS
24
18
12
3
Q3
0
02
ID = 3 A
TJ = 25°C
4 6 8 10
Qg, TOTAL GATE CHARGE (nC)
6
0
12
Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
3.0
TJ = 25°C
VGS = 0 V
2.5
2.0
1.5
1.0
0.5
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage
versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
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