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PDF MM74HC595M Data sheet ( Hoja de datos )
| Número de pieza | MM74HC595M | |
| Descripción | 8-Bit Shift Registers with Output Latches | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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September 1983
Revised February 1999
MM74HC595
8-Bit Shift Registers with Output Latches
General Description
The MM74HC595 high speed shift register utilizes
advanced silicon-gate CMOS technology. This device pos-
sesses the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has 8 3-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge trig-
gered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s 8-bit serial-in, parallel-out shift register with storage
s Wide operating voltage range: 2V–6V
s Cascadable
s Shift register has direct clear
s Guaranteed shift frequency: DC to 30 MHz
Ordering Code:
Order Number Package Number
Package Description
MM74HC595M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC595WM
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC595SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC595MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC595N
N16E
16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
RCK SCK
XX
XX
X↑
↑X
SCLR
X
L
H
H
G Function
H QA thru QH = 3-STATE
L Shift Register cleared
QH = 0
L Shift Register clocked
QN = Qn-1, Q0 = SER
L Contents of Shift
Register transferred
to output latches
Top View
© 1999 Fairchild Semiconductor Corporation DS005342.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C Units
Typ Guaranteed Limits
tPZH, tPZL Maximum Output Enable
from G to QA thru QH
tPHZ, tPLZ Maximum Output Disable
Time from G to QA thru QH
RL = 1 kΩ
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
RL = 1 kΩ
CL = 50 pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
75
100
15
20
13
17
75
15
13
175
245
35
49
30
42
175
35
30
220
306
44
61
37
53
220
44
37
265 ns
368 ns
53 ns
74 ns
45 ns
63 ns
265 ns
53 ns
45 ns
tS Minimum Setup Time
from SER to SCK
2.0V
4.5V
100 125
20 25
150 ns
30 ns
6.0V
17 21
25 ns
tR Minimum Removal Time
from SCLR to SCK
2.0V
4.5V
50 63
10 13
75 ns
15 ns
6.0V
9 11
13 ns
tS Minimum Setup Time
from SCK to RCK
2.0V
4.5V
100 125
20 25
150 ns
30 ns
6.0V
17 21
26 ns
tH Minimum Hold Time
SER to SCK
2.0V
4.5V
55
55
5 ns
5 ns
6.0V
55
5 ns
tW Minimum Pulse Width
of SCK or SCLR
2.0V
4.5V
30
9
80
16
100
20
120 ns
24 ns
6.0V
8
14
18
22 ns
tr, tf Maximum Input Rise and
Fall Time, Clock
2.0V
4.5V
1000
500
1000
500
1000
500
ns
ns
6.0V
400 400
400 ns
tTHL, tTLH Maximum Output
Rise and Fall Time
2.0V
4.5V
25
7
60
12
75
15
90 ns
18 ns
tTHL, tTLH
QA–QH
Maximum Output
Rise & Fall Time
6.0V
2.0V
4.5V
6
10
75
15
13
95
19
15 ns
110 ns
22 ns
QH
CPD Power Dissipation
Capacitance, Outputs
G = VCC
G = GND
6.0V
90
150
13
16
19 ns
pF
pF
Enabled (Note 6)
CIN Maximum Input
Capacitance
5 10
10
10 pF
COUT
Maximum Output
Capacitance
15 20
20
20 pF
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MM74HC595M.PDF ] | |
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