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PDF MAX5858 Data sheet ( Hoja de datos )
| Número de pieza | MAX5858 | |
| Descripción | Dual / 10-Bit / 300Msps / Current-Output DAC with 4x/2x/1x Interpolation Filters | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX5858 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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19-2879; Rev 0; 7/03
EVAALVUAAILTAIOBNLEKIT
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
General Description
The MAX5858 dual, 10-bit, 300Msps digital-to-analog con-
verter (DAC) provides superior dynamic performance in
wideband communication systems. The MAX5858 inte-
grates two 10-bit DAC cores, 2x/4x programmable digital
interpolation filters, and a 1.24V reference. The MAX5858
supports single-ended and differential modes of operation.
The MAX5858 dynamic performance is maintained over
the entire power-supply operating range of 2.7V to 3.3V.
The analog outputs support a compliance voltage of -1.0V
to +1.25V.
The 4x/2x programmable interpolation filters feature
excellent passband distortion and noise performance.
Interpolating filters minimize the design complexity of
analog reconstruction filters while lowering data bus
and clock speeds of the digital interface. To reduce the
I/O pin count, the DAC can also operate in interleave
data mode. This allows the MAX5858 to be updated on
a single 10-bit bus.
The MAX5858 features digital control of channel gain
matching to within ±0.4dB in 16 0.05dB steps. Channel
matching improves sideband suppression in analog
quadrature modulation applications. The on-chip 1.24V
bandgap reference includes a control amplifier that
allows external full-scale adjustments of both channels
through a single resistor. The internal reference can be
disabled and an external reference may be applied for
high-accuracy applications.
The MAX5858 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.3V single sup-
ply. The DAC supports three modes of power-control
operation: normal, low-power standby, and complete
power-down. In power-down mode, the operating
current is reduced to 1µA.
The MAX5858 is packaged in a 48-pin TQFP with exposed
paddle (EP) for enhanced thermal dissipation and is spec-
ified for the extended (-40°C to +85°C) temperature range.
Applications
Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Direct Digital Synthesis
Instrumentation/ATE
Features
o 10-Bit Resolution, Dual DAC
o 300Msps Update Rate
o Integrated 4x/2x Interpolating Filters
o 2.7V to 3.3V Single Supply
o Full Output Swing and Dynamic Performance at
2.7V Supply
o Superior Dynamic Performance
75dBc SFDR at fOUT = 20MHz
UMTS ACLR = 63dB at fOUT = 30.7MHz
o Programmable Channel-Gain Matching
o Integrated 1.24V Low-Noise Bandgap Reference
o Single-Resistor Gain Control
o Interleave Data Mode
o Differential Clock Input Modes
o EV Kit Available—MAX5858 EV Kit
Ordering Information
PART
MAX5858ECM
*EP = Exposed paddle.
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
1 DA9/PD
2 DA8/DACEN
3 DA7/F2EN
4 DA6/F1EN
5 DA5/G3
6 DGND
7 DVDD
8 DA4/G2
9 DA3/G1
10 DA2/G0
11 DA1
12 DA0
MAX5858
REFO 36
REN 35
I.C. 34
CGND 33
CVDD 32
CLKXN 31
CLKXP 30
CGND 29
I.C. 28
CW 27
DB0 26
DB1 25
13 14 15 16 17 18 19 20 21 22 23 24
TQFP-EP
NOTE: EXPOSED PADDLE CONNECTED TO GND.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
DATA-to-CLK Rise Setup Time
DATA-to-CLK Rise Hold Time
DATA-to-CLK Fall Setup Time
DATA-to-CLK Fall Hold Time
Control Word to CW Fall Setup
Time
SYMBOL
tDCSR
tDCHR
tDCSF
tDCHF
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tCWS
CONDITIONS
MIN TYP MAX UNITS
1.5 ns
0.4 ns
1.7 ns
1.1 ns
2.5 ns
Control Word to CW Fall Hold
Time
CW High Time
CW Low Time
DACEN Rise-to-VOUT Stable
PD Fall-to-VOUT Stable
Clock Frequency at
CLKXP/CLKXN Input
tCWH
tSTB
tPDSTB
fDAC
External reference
Differential clock
2.5 ns
5
5
0.7
0.5
ns
ns
µs
ms
300 MHz
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
tCXD
4.6 ns
Minimum CLKXP/CLKXN Clock
High Time
tCXH
1.5 ns
Minimum CLKXP/CLKXN Clock
Low Time
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
tCXL
AVDD
IAVDD
DVDD
(Note 4)
1.5 ns
2.7 3.3 V
45 49 mA
2.7 3.3 V
_______________________________________________________________________________________ 5
5 Page 
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V ±10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS = 20mA, differential
output, TA = +25°C, unless otherwise noted.)
ACLR WITH UMTS PLOT
(NO INTERPOLATION, fDAC = 122.88MHz,
fDATA = 122.88MHz, fCENTER = 30.72MHz)
-25
-30 ACLR = 63dB
-40
-50
-60
-70
-80
-90
-100
-110
-120
-125
0
12.288MHz/div
OUTPUT FREQUENCY (MHz)
122.88
ACLR WITH UMTS PLOT
(2x INTERPOLATION, fDAC = 245.76MHz,
fDATA = 122.88MHz, fCENTER = 30.72MHz)
-25
-30
-40 ACLR = 63dB
-50
-60
-70
-80
-90
-100
-110
-120
-125
0
6.14MHz/div
OUTPUT FREQUENCY (MHz)
61.44
ACLR WITH UMTS PLOT
(2x INTERPOLATION, fDAC = 245.76MHz,
fDATA = 122.88MHz, fCENTER = 30.72MHz)
-25
-30
-40 ACLR = 63dB
-50
-60
-70
-80
-90
-100
-110
-120
-125
0
12.288MHz/div
OUTPUT FREQUENCY (MHz)
122.88
PIN
1
2
3
4
5
6, 19, 47
7, 18, 48
8
9
Pin Description
NAME
FUNCTION
DA9/PD
Channel A Input Data Bit 9 (MSB)/Power-Down Control Bit:
0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1).
1: Enter power-down mode.
DA8/DACEN
Channel A Input Data Bit 8/DAC Enable Control Bit:
0: Enter DAC standby mode with PD = 0.
1: Power up DAC with PD = 0.
X: Enter power-down mode with PD = 1 (X = don’t care).
DA7/F2EN
Channel A Input Data Bit 7/Second Interpolation Filter Enable Bit:
0: Interpolation mode is determined by F1EN.
Enable 4x interpolation mode. (F1EN must equal 1.)
DA6/F1EN
Channel A Input Data Bit 6/First Interpolation Filter Enable Bit:
0: Interpolation disable.
1: Enable 2x interpolation.
DA5/G3 Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3
DGND Digital Ground
DVDD
DA4/G2
Digital Power Supply. See the Power Supplies, Bypassing, Decoupling, and Layout section.
Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2
DA3/G1 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MAX5858.PDF ] | |
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