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PDF MAX5856AECM Data sheet ( Hoja de datos )
| Número de pieza | MAX5856AECM | |
| Descripción | Dual 8-Bit / 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL | |
| Fabricantes | Maxim Integrated | |
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19-3019; Rev 0; 10/03
EVAALVUAAILTAIOBNLEKIT
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
General Description
The MAX5856A dual, 8-bit, 300Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The MAX5856A
integrates two 8-bit DAC cores, 4x/2x/1x programmable
digital interpolation filters, phase-lock loop (PLL) clock
multiplier, and a 1.24V reference. The MAX5856A sup-
ports single-ended and differential modes of operation.
The MAX5856A dynamic performance is maintained over
the entire power-supply operating range of 2.7V to 3.3V.
The analog outputs support a compliance voltage of
-1.0V to +1.25V.
The 4x/2x/1x programmable interpolation filters feature
excellent passband distortion and noise performance.
Interpolating filters minimize the design complexity of ana-
log reconstruction filters while lowering the data bus and
the clock speeds of the digital interface. The PLL multiplier
generates all internal synchronized high-speed clock sig-
nals for interpolating filter operation and DAC core conver-
sion. The internal PLL helps minimize system complexity
and lower cost. To reduce the I/O pin count, the DAC can
also operate in interleave data mode. This allows the
MAX5856A to be updated on a single 8-bit bus.
The MAX5856A features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-chip
1.24V bandgap reference includes a control amplifier
that allows external full-scale adjustments of both chan-
nels through a single resistor. The internal reference can
be disabled and an external reference may be applied
for high-accuracy applications.
The MAX5856A features full-scale current outputs of
2mA to 20mA and operates from a 2.7V to 3.3V single
supply. The DAC supports three modes of power-control
operation: normal, low-power standby, and complete
power-down. In power-down mode, the operating cur-
rent is reduced to 1µA.
The MAX5856A is packaged in a 48-pin TQFP with
exposed paddle (EP) for enhanced thermal dissipation
and is specified for the extended (-40°C to +85°C) opera-
ting temperature range.
Applications
Communications
SATCOM, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Direct Digital Synthesis
Instrumentation/ATE
Features
o 8-Bit Resolution, Dual DAC
o 300Msps Update Rate
o Integrated 4x/2x/1x Interpolating Filters
o Internal PLL Multiplier
o 2.7V to 3.3V Single Supply
o Full Output Swing and Dynamic Performance at
2.7V Supply
o Superior Dynamic Performance: 68dBc SFDR at
fOUT = 20MHz
o Programmable Channel Gain Matching
o Integrated 1.24V Low-Noise Bandgap Reference
o Single-Resistor Gain Control
o Interleave Data Mode
o Differential Clock Input Modes
o EV Kit Available—MAX5858AEVKIT
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX5856AECM
-40°C to +85°C 48 TQFP-EP*
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
DA7/PD 1
DA6/DACEN 2
DA5/F2EN 3
DA4/F1EN 4
DA3/G3 5
DGND 6
DVDD 7
DA2/G2 8
DA1/G1 9
DA0/G0 10
N.C. 11
N.C. 12
EP
MAX5856A
36 REF0
35 REN
34 PLLF
33 PGND
32 PVDD
31 CLKXN
30 CLKXP
29 PLLEN
28 LOCK
27 CW
26 N.C.
25 N.C.
13 14 15 16 17 18 19 20 21 22 23 24
TQFP-EP
NOTE: EXPOSED PADDLE CONNECTED TO GND.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference,
VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C,
guaranteed by production test. TA < +25°C, guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
Clock Frequency at CLK Input
Output Settling Time
Output Rise Time
Output Fall Time
Data-to-CLK Rise Setup Time
(Note 3)
Data-to-CLK Rise Hold Time
(Note 3)
Data-to-CLK Fall Setup Time
(Note 3)
Data-to-CLK Fall Hold Time
(Note 3)
Control Word to CW Fall Setup
Time
SYMBOL
fCLK
ts
tDCSR
tDCHR
tDCSF
tDCHF
CONDITIONS
No interpolation, PLL enabled
2x interpolation, PLL enabled
4x interpolation, PLL enabled
To ±0.1% error band (Note 2)
10% to 90% (Note 2)
90% to 10% (Note 2)
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
tCWS
MIN TYP MAX UNITS
165
75 150 MHz
37.5 75
11 ns
2.5 ns
2.5 ns
1.5
ns
2.2
0.4
ns
1.4
1.8
ns
2.4
1.2
ns
1.3
2.5 ns
Control Word to CW Fall Hold
Time
CW High Time
CW Low Time
DACEN Rise-to-VOUT Stable
PD Fall-to-VOUT Stable
Clock Frequency at
CLKXP/CLKXN Input
tCWH
tSTB
tPDSTB
External reference
fCLKDIFF Differential clock, PLL disabled
2.5 ns
5
5
0.7
0.5
ns
ns
µs
ms
300 MHz
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
tCXD PLL disabled
4.6 ns
Minimum CLKXP/CLKXN Clock
High Time
tCXH
1.5 ns
Minimum CLKXP/CLKXN Clock
Low Time
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
tCXL
AVDD
IAVDD
DVDD
(Note 4)
1.5 ns
2.7 3.3 V
44 47 mA
2.7 3.3 V
_______________________________________________________________________________________ 5
5 Page 
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
Typical Operating Characteristics (continued)
(AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA,
differential output, TA = +25°C, unless otherwise noted.)
DYNAMIC RESPONSE RISE TIME
MAX5856A toc29
DYNAMIC RESPONSE FALL TIME
MAX5856A toc30
200mV/div
200mV/div
RL = 50Ω
SINGLE ENDED
10ns/div
RL = 50Ω
SINGLE ENDED
10ns/div
Pin Description
PIN NAME
FUNCTION
Channel A Input Data Bit 7 (MSB)/Power-Down Control Bit:
1 DA7/PD 0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1).
1: Enter power-down mode.
Channel A Input Data Bit 6/DAC Enable Control Bit:
2
DA6/DACEN
0: Enter DAC standby mode with PD = 0.
1: Power up DAC with PD = 0.
X: Enter power-down mode with PD = 1 (X = don’t care).
Channel A Input Data Bit 5/Second Interpolation Filter Enable Bit:
3 DA5/F2EN 0: Interpolation mode is determined by F1EN.
1: Enable 4x interpolation mode. (F1EN must equal 1.)
4
5
6, 19, 47
7, 18, 48
8
9
10
11, 12, 25,
26, 37, 38
13
14
DA4/F1EN
DA3/G3
DGND
DVDD
DA2/G2
DA1/G1
DA0/G0
Channel A Input Data Bit 4/First Interpolation Filter Enable Bit:
0: Interpolation disable.
1: Enable 2x interpolation.
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3
Digital Ground
Digital Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section.
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2
Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1
Channel A Input Data Bit 0/Channel A Gain Adjustment Bit 0
N.C.
No Connection. Not connected internally.
DB7
DB6
Channel B Input Data Bit 7 (MSB)
Channel B Input Data Bit 6
______________________________________________________________________________________ 11
11 Page | ||
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| PDF Descargar | [ Datasheet MAX5856AECM.PDF ] | |
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