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PDF MC10E111 Data sheet ( Hoja de datos )
| Número de pieza | MC10E111 | |
| Descripción | 1:9 DIFFERENTIAL CLOCK DRIVER | |
| Fabricantes | ON Semiconductor | |
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MC10E111, MC100E111
5 V ECL 1:9 Differential
Clock Driver
Description
The MC10E/100E111 is a low skew 1-to-9 differential driver,
designed with clock distribution in mind. It accepts one signal input,
which can be either differential or else single-ended if the VBB output
is used. The signal is fanned out to 9 identical differential outputs. An
enable input is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q outputs HIGH.
The device is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within-device, and empirical modeling is used to
determine process control limits that ensure consistent tpd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10–20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10–20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
• Guaranteed Skew Spec
• Differential Design
• VBB Output
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
• Internal Input 50 KW Pulldown Resistors
• ESD Protection: > 3 kV Human Body Model
• Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 178 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 17
1
www.onsemi.com
PLCC−28
FN SUFFIX
CASE 776−02
MARKING DIAGRAM*
1
MCxxxE111G
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC10E111FNG
MC10E111FNR2G
MC100E111FNG
MC100E111FNR2G
Package
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
Shipping†
37 Units/Tube
500 Tape & Reel
37 Units/Tube
500 Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC10E111/D
1 page  
MC10E111, MC100E111
Table 6. 100E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOL
VIH
VIL
VBB
VIHCMR
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
40 60
45 60
50 69
−1025 −980 −880 −1025 −980 −880 −1025 −980 −880
−1810 −1700 −1620 −1810 −1700 −1620 −1810 −1700 −1620
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475
−1.38
−1.25 −1.38
−1.26 −1.38
−1.26
−1.6 −0.4 −1.6 −0.4 −1.6 −0.4
mA
mV
mV
mV
mV
V
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5
0.5 0.25
0.5 0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V
3. VIHCMR min and max vary 1:1 with VCC.
Table 7. AC CHARACTERISTICS (VCCx = 5.0 V; VEE= 0.0 V or VCCx = 0.0 V; VEE= −5.0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
fMAX
tPLH
tPHL
Maximum Toggle Frequency
Propagation Delay to Output
IN (Diff) (Note 2)
IN (SE) (Note 3)
Enable (Note 4)
Disable (Note 4)
800 800 800 MHz
ps
430 630 430 630 430 630
380 680 380 680 380 680
400 900 450 850 450 850
400 900 450 850 450 850
ts Setup Time (Note 5)
EN to IN
250 0
200 0
200 0
ps
tH Hold Time (Note 6)
IN to EN
50 −200
0 −200
0 −200
ps
tR Release Time (Note 7)
EN to IN
350 100
300 100
300 100
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 / +0.8 V.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of
the differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition
on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the
50% point of a negative transition on Q (or a positive transition on Q).
5. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than $75 mV to that IN/IN transition (Figure 3).
6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output
response greater than $75 mV to that IN/IN transition (Figure 4).
7. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (Figure 5).
8. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
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| PDF Descargar | [ Datasheet MC10E111.PDF ] | |
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