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PDF CXD1961Q Data sheet ( Hoja de datos )
| Número de pieza | CXD1961Q | |
| Descripción | DVB-S Front-end IC (QPSK demodulator + FEC) | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CXD1961Q (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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CXD1961Q
DVB-S Front-end IC (QPSK demodulator + FEC) Preliminary
For the availability of this product, please contact the sales office.
Description
The CXD1961Q is a single chip DVB Satellite
100 pin QFP (Plastic)
Broadcasting Front-end IC, including dual ADC for
analog I/O inputs, QPSK demodulator, Viterbi
decoder, de-interleaver, Reed-Solomon decoder
and Energy Dispersal descrambler.
It is suitable for use in a DVB Integrated Receiver
Decoder.
Features
• Dual 6 bit A/D converters
• QPSK demodulator
Multi-symbol rate operation
Nyquist roll off filter (α = 0.35)
Clock recovery circuit
Carrier recovery circuit
AGC control circuit
• Viterbi decoder
Constraint length K =7
Punctured rate R = 1/2 –7/8
Truncation length 144
Punctured rate search function
BER monitor
• De-interleaver
Packet synchronization
Convolutional de-interleaver
• Reed-Solomon decoder (204, 188)
• Energy dispersal descrambler
• CPU interface
l2C bus interface/8 bit CPU bus
TTL interface level (5V input capability)
• JTAG(IEEE std 1149.1–1990) test mode
• Package : QFP-100pin
• Single +3.3V Power Supply
• Symbol rate max:32MSPS min:TBD
• Power consumption TBD
• 0.4um CMOS Technology
Absolute Maximum Ratings (Ta=25°C, GND=0V)
• Supply voltage
VDD –0.5 to 4.6 V
• Input voltage
VIN –0.5 to VDD+0.5 V
• Output voltage
VOUT –0.5 to VDD+0.5 V
• I/O voltage
VI/O –0.5 to VDD+0.5 V
• CPU I/F pin
VCPUIF –0.5 to 5.5 V
• Operating temperature Topr
0 to +75 °C
• Storage temperature Tstg –55 to +150 °C
DC Recommended Operating Conditions
(Ta=0°C to 75°C, GND=0 V)
• Supply voltage
VDD 3.15 to 3.45 V
• Input Hi-level
VIH VDD–0.7 to VDD+0.5 V
• Input Lo-level
VIL 0.3 to VDD +0.2 V
Applications
• DVB-S Set Top Box (Satellite)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
PE96417-TE
1 page  
No.
Symbol
I/O
Description
55–57
ADD1–3
I 8 bit CPU bus Address1–3 (ADD3 : MSB)
58 SCL I I2C bus serial clock
59
SDA
I/O I2C bus serial data
60
VDD7
— Digital Power Supply (+3.3 V)
61
VSS7
— Digital Ground
62 XO O Oscillator output (for Crystal)
63 XI I Oscillator input (for Crystal)
64, 65
TEST4, 5
O Test output (VSS level)
66
VDD8
— Digital Power Supply (+3.3 V)
67
VSS8
— Digital Ground
68
AGCPWM
O PWM output for AGC
69
CKV
O Sampling Clock monitor output
70–73
CR0–3
O Clock Recovery data 0–3 (CR0 : LSB)
74
VDD9
— Digital Power Supply (+3.3 V)
75
VSS9
— Digital Ground
76–79
CR4–7
O Clock Recovery data 4–7 (CR7 : MSB)
80
VDD10
— Digital Power Supply (+3.3 V)
81
VSS10
— Digital Ground
82, 83
TEST6, 7
O Test output (VSS level)
84
VDD11
— Digital Power Supply (+3.3 V)
85
VSS11
— Digital Ground
86
CPOUT
O PLL Charge pump output
87
AVD2
— Analog Power Supply (+3.3 V)
88
VCOC
I VCO control voltage input
89
OPXIN
I Embedded OP-Amp Negative input
90
OPOUT
O Embedded OP-Amp output
91
AVS2
— Analog Ground
92
VCOEN
I VCO enable (H : enable)
93 RT1 — ADC1 top reference voltage
94
AVD1
— Analog Power Supply (+3.3 V)
95 QIN I Analog Q input (ADC1 input)
96
AVS1
— Analog Ground
97 RB1 — ADC1 bottom reference voltage
98 RT0 — ADC0 top reference voltage
99
AVD0
— Analog Power Supply (+3.3 V)
100 IIN I Analog input (ADC0 input)
Note)
Apply 0.1 µF capacitor to every power supply terminal.
Apply 0.1µF capacitor to RB0, RT0, RB1, RT1 for stable A to D conversion.
CXD1961Q
—5—
5 Page 
CXD1961Q
(2) Analog to Digital Converters
The Dual 6 bit A to D converters quantize the analog I/Q input data. The input range of the ADC's is
determined by external resistors. RT0 (RT1) is the top reference voltage, and RB0 (RB1) is the bottom
reference voltage. RT0 (RT1) and RB0 (RB1) are connected internally with a 320 Ω (Typical value) resistor.
In the example shown in the following figure, input range is approximately 1.1 V, and center voltage 1.65 V.
AVD (+3.3V)
330Ω
CXD1961Q
RT Top reference level
330Ω
320Ω
Input range
RB Bottom reference level
AVS (0V)
(3) AGC
Input signal level of the A to D Converter is estimated by calculating I2+Q2 in 16 bit precision, and the upper
8 bits of the estimated data are sent via the CPU I/F as ADC_IN [7:0]. CXD1961Q has two AGC modes that
can be selected by AGC_MOD. In AGC slave mode, ADC_IN[7:0] is checked and an appropriate gain level
AGC[7:0] is returned by the micro controller. This value is converted into 8 bit PWM format and output from
AGCPWM (Pin 68).
In AGC master mode, reference level AGC[7:0] is set via the CPU I/F and compared to ADC_IN[7:0]
internally. The updated gain level is then output at the AGCPWM pin. In normal operation, ADC_IN[7:0]
becomes almost equal to reference level. In AGC master mode, AGC control interval is set by TIMER[2:0].
In both modes, AGCPWM output should be low pass filtered, and if needed, the level should be converted
to satisfy the AGC gain control range. Depending on AGC_INV, the polarity can be inverted. (H:positive /
L:negative)
CPU Register
ADC_IN [7 : 0] →
AGC_MOD
→
Reference level
ADC_IN [7 : 0]
0F
3F
7F
FF
ADD 0h
AGC [7 : 0] →
ADD 7h
TIMER [2 : 0] →
Input signal level
to ADC input range ratio
0.25
0.5
0.7
1.0 or over range
ADD 4h
ADD 7h
AGC_INV
→ ADD 7h
Note)
ADC input range is subject to temperature and VDD level.
—11—
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CXD1961Q.PDF ] | |
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