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PDF CXD1961AQ Data sheet ( Hoja de datos )
| Número de pieza | CXD1961AQ | |
| Descripción | DVB-S Frontend IC (QPSK demodulation + FEC) | |
| Fabricantes | Sony Corporation | |
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CXD1961AQ
DVB-S Frontend IC (QPSK demodulation + FEC) Preliminary
For the availability of this product, please contact the sales office.
Description
The CXD1961AQ is a single chip DVB compliant
Satellite Broadcasting Frontend IC, including dual
A/D converter for analog baseband I/Q input, QPSK
demodulator, Viterbi decoder Reed-Solomon decoder
and Energy Dispersal descrambler. It is suitable for
use in a DVB Integrated Receiver Decoder.
100 pin QFP (Plastic)
Features
• Dual 6 bit A/D converter
• QPSK demodulator
Multi-symbol rate operation
Nyquist Roll off filter (α = 0.35)
Clock recovery circuit
Carrier recovery circuit
AGC control (PWM output)
• Viterbi decoder
Absolute Maximum Rating (Ta = 25°C, GND = 0V)
• Power Supply
VDD –0.5 to +4.6 V
• Input Voltage
VIN –0.5 to VDD + 0.5 V
• Output Voltage
VOUT –0.5 to VDD + 0.5 V
• I/O Voltage
VI/O –0.5 to VDD + 0.5 V
• CPU I/F pin
Vcpuif –0.5 to +5.5 V
• Storage Temperature Tstg –55 to +150 °C
Constraint length 7
Truncation length 144
BER monitor of QPSK demodulator output
• Frame synchronization circuit
• Convolutional de-interleaver
• Reed-Solomon decoder (204,188)
Recommended Operating Condition
(Ta = 0 to 75°C, GND = 0V)
• Power Supply
VDD 3.15 to 3.45 V
• Input High level
VIH 0.7 × VDD to VDD + 0.5 V
• Input Low level
VIL 0.3 to 0.2 × VDD V
BER monitor of Viterbi decoder output
• Energy dispersal descrambler
• CPU interface circuit
I2C bus interface (5V input capability)
• Package
QFP 100pin
• Operating frequency 20 to 30MSPS
• Power consumption 750mW (@3.3V 30MSPS typical)
• Process
0.4µm CMOS Technology
Application
DVB-S Set Top Box (Satellite)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE97854-PS
1 page  
CXD1961AQ
(10) CPU Interface
The CXD1961AQ has an I2C bus interface. Serial clock SCL is Pin 58 and serial data in out SDA is Pin 59.
Slave address is "1101 111" (DChex).
<Write data>
During the write operation, the second byte is input as the sub-address of the start position. The third byte then
forms the data to be written to the start register. Successive data bytes are written to the successive sub-
address registers up to 21 (hex). Note that registers of sub-addresses 00 (hex) to 0B (hex) are read only.
Slave address
1101 111
0
STA: start condition
STP: stop condition
Sub address
N (hex)
Input data for
sub-address
N (hex)
Input data for
sub-address
N + 1 (hex)
ACK: acknowledge
XACK: no acknowledge
···
<Read operation>
Before the read operation, the sub-address of the start register to be read is input by using write operation, and
terminated with a stop condition. Read operation then begins with the second byte which is the data of the start
register. Data of the successive sub-address registers are read successively following the second byte. All
registers can be read.
Slave address
1101 111
0
Sub address
N (hex)
Slave address
1101 111
1
Output data for
sub-address
N (hex)
Both SCL and SDA have 5V input capability.
Output data for
sub-address
N + 1 (hex)
···
–5–
5 Page 
2-3. Clock Recovery
Function
Clock error output
(for clock recovery by VCXO)
Recovered symbol clock output
(switchable to sampling clock output)
3. Carrier Recovery
Function
Carrier lock flag (H: lock)
4. AGC
Function
AGC control data (PWM output)
See reference circuit (4)
Pin No. Pin name
70 to 73 CR0 to 3
76 to 79 CR4 to 7
69 CKV
Pin No. Pin name
82 QSYNC
Pin No. Pin name
68 AGCPWM
5. Viterbi Decoder
Function
Viterbi clock output
Viterbi decoded data output
Pin No.
65
64
Pin name
VCK
VDT
These pins can be fixed to ground by setting CPU I/F register 0E (hex).
6. Frame Synchronization
Function
Frame synchronization flag (H: sync)
Pin No. Pin name
83 FSYNC
CXD1961AQ
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1961AQ.PDF ] | |
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