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PDF CY7C955 Data sheet ( Hoja de datos )
| Número de pieza | CY7C955 | |
| Descripción | AX ATM-SONET/SDH Transceiver | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY7C955
AX™ ATM-SONET/SDH Transceiver
Features
• WAN and LAN ATM physical layer device
• Provides complete physical layer transport of ATM cells
at:
— STS−3c/ STM−1 rate of 155.52 MHz
— STS−1 rate of 51.84 MHz
• Compliant with ATM Forum User Network Interface 3.1
specification
• UTOPIA ATM interface
• ATM cell processing including:
— HEC generation/verification
— Cell scrambling/descrambling
— Rate adaption/idle cell filtering
— Local Flow Control
— Cell alignment
• SONET frame processing including:
— Compliant with Bellcore GR−253, I.432,
T1.105, and G.709 for Jitter Tolerance and Jitter
Generation
— Frame generation/recovery
— SONET scrambling/descrambling
— Frequency justification/pointer processing
• Complete line interface including:
— Clock and data recovery
— Transmit timing derived from receiver or byte-rate
source
— SONET compliant PLL
— 100K PECL compatible I/O
• Alarm indications including:
— Loss Of Signal
— Out Of Frame, Loss Of Frame
— Line Far End Receive Failure
— Line Alarm Indication Signal
— B1 Parity Error
— Loss Of Cell Alignment
— Loss Of Receive Data
• Controller interface for internal interrupt and
configuration registers including:
— Error monitoring
— Status indication
— Device configuration
• 0.65µ Low Power CMOS
• 128-pin PQFP
Functional Description
The Cypress Semiconductor CY7C955 is a Transceiver chip
designed to carry ATM cells across SONET/SDH systems.
On the transmit side, ATM cells coming from the Utopia inter-
face are being mapped into SONET/SDH frames and then se-
rialized for transmission over fiber or twisted pair (through an
optical module or an equalizer chip).
On the receive side, serial SONET/SDH datastreams coming
from an optical module or an equalizer chip are being recov-
ered by the intergrated clock and data recovery phase-locked
loop, framed, processed, and presented as parallel ATM cells
on the Receive Utopia Interface.
The CY7C955 can be used in a Network Interface Card (NIC)
design to connect the segmentation and Reassembly (SAR)
chip to the optical modules or equalizer chip.
The CY7C955 can also be used in work group or enterprise
switches to connect the I/O FIFOs of the switch fabric to the
optical module or equalizer in the interface boards.
The applications of the CY7C955 include adapters, switches,
routers, hubs, and proprietary systems.
Features
Functional Description
Pin Descriptions
Pin Configuration
Description
Transmit Section
Receive Section
Controller Interface (CI)
Loopback Operation
SONET Overhead Description
CY7C955 Register Map
Electrical Characteristics
Capacitance
AC Test Loads and Waveforms
Switching Characteristics
TABLE OF CONTENTS
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 29, 1999
1 page  
PRELIMINARY
CY7C955
Receive Utopia Interface (continued)
Name
TSEN
Pin No I/O
66 Input
Description
Receive Output Enable: This output operates in conjunction with the RRDENB output.
When TSEN is HIGH and RRDENB is HIGH the Receive UTOPIA data bus (RDAT[7:0],
RPRTY, and RSOC) is three-stated. When TSEN is HIGH and RRDENB is LOW the
data bus is driven with the requested data. When TSEN is LOW the data bus will not
three-state.
Controller Interface
Name
D[7:0]
A[7:0]
ALE
Pin No
110−112
115−118
119−126
127
RDB
WRB
CSB
INTB
105
104
100
108
ALOS±
27−28
RSTB
101
VCLK
99
I/O
I/O
Input
Input
Input
Input
Input
Output
Differential In
Input
Input
Description
Data[7:0]: Bidirectional data bus used to transfer data to and from the internal config-
uration, status, and error monitoring registers.
Address[7:0]: Address bus used to select the internal register for reading or writing.
Address Latch Enable: When this input is LOW the address is latched from the A[7:0]
inputs. When this input is HIGH, the input is transparent. ALE has an integrated pull-
up resistor.
Read: This active LOW signal is used to read the internal register. The AX drives D[7:0]
when RDB and CSB are both LOW.
Write: This active LOW signal is used to write the internal registers. Data is latched
into the specified address register on the rising edge of WRB when CSB is LOW.
Select: This active LOW device select has to be enabled during register accesses.
Interrupt: This active LOW open drain output transitions LOW when an unmasked
interrupt source is active. This output transitions HIGH when the appropriate register
has been read. This interrupt signals the most critical error states of the device includ-
ing Loss of Pointer, Line Alarm Indication Signal (LAIS), Line Far End Receive Failure
(LFERF), Loss of Frame (LOF), Out of Frame (OOF), Loss of Signal (LOS), and many
others.
Carrier Detect: This differential input controls the recovery function of the Receive PLL
and can be driven by the carrier detect output from optical modules or from external
transition detection circuitry. When this input is at a Logic Low, the input data stream
(RXD±) is recovered normally by the Receive Clock Recovery PLL. When this input is
at a Logic High, the Receive PLL no longer aligns to RXD±, but instead aligns with the
RRCLK * 8 frequency and the LOS alarm register (RDOOLV) will be set. Besides
differential PECL, the ALOS− input can be set to accept single ended PECL input if
ALOS+ is tied to GND. ALOS− has to be decoupled.
Reset: This active LOW signal provides a device reset. This line can be pulled LOW
to put the CY7C955 into the power-down mode. RSTB has an integrated pull-up resis-
tor.
Factory test pin. Must be LOW for normal operation. VCLK has an integrated pull-down
resistor.
Transmit Power
Name
Pin No
TXVDD
12
I/O
Power
TAVD1
TAVD2
TAVD3
TVDDO
4
6
8
18
Power
Power
Power
Power
Description
The Transmit Pad Power supplies the TXD± outputs. TXVDD is physically isolated from
the other device power pins and should be well regulated +5V DC and noise-free for good
performance when driving category 5 unshielded twist pair cabling.
The power pin for the transmit clock synthesizer reference circuitry. TAVD1 should be
connected to analog +5V.
The power pin for the transmit clock synthesizer oscillator. TAVD2 should be connected
to analog +5V.
The power pin for the transmit PECL inputs. TAVD3 should be connected to analog +5V.
Power for TXC± and RXDO±.
5
5 Page 
PRELIMINARY
CY7C955
(LOF) is declared when the OOF condition fails to clear within
3 ms. LOF clears after 3 ms of frames with valid framing char-
acters.
Receive SONET Section Overhead Processor (RSOP)
The RSOP provides descrambling, SONET section alarm in-
dication, and error monitoring.
The data is descrambled using the generating polynomial 1 +
x6 + x7. The A1, A2, and C1 bytes are not descrambled. The
scrambling process may be disabled under register control.
The BIP−8 value calculated over the previous scrambled frame
is compared with the B1 byte of the current frame section over-
head after descrambling. If the two values do not match, the
B1PAR output is taken HIGH. Up to 64,000 errors can be de-
tected per second (8000 frames/second * 8 bit-errors
(max)/frame). Errors are recorded in a 16-bit saturating
counter that can be read through the controller interface.
Receive SONET Line Overhead Processor (RLOP)
The RLOP provides SONET line alarm indications and error
monitoring.
A Line Alarm Indication Signal (LAIS) is asserted when a 111
pattern is detected for five consecutive frames in bits 6,7, and
8 of the first K2 byte of the Automatic Protection Switching
channel. LAIS is removed when anything other than a 111 pat-
tern is received for five consecutive frames.
A Line Far End Receive Failure (LFERF) or Line RDI is indi-
cated with a 110 pattern is detected for five consecutive frames
in bits 6,7, and 8 of the first K2 byte. LFERF is removed when
anything other than a 110 pattern is received for five consec-
utive frames.
The BIP−24 (BIP−8 for STS−1 RATE) value calculated over the
previous line overhead and SPE is compared with the B2 bytes
of current frame. Up to 192,000 errors can be detected per
second (3 channels/frame * 8 errors (max)/channel * 8000
frames/second). Errors are recorded in a 20-bit saturating
counter that can be read through the controller interface.
Far End Block Errors (FEBE) are detected by examining the
value in the third Z2 byte. This value (0−18h) is added to the
count in an 18-bit saturating counter that can be read through
the controller interface.
Receive SONET Path Overhead Processor (RPOP)
The RPOP provides pointer interpretation, SPE extraction,
SONET path alarm indications, and error monitoring.
The payload location is determined by examining the values in
the H1 and H2 bytes of the line overhead which indicate the J1
byte of the SPE. The RPOP can process a J1 byte located
anywhere in the SPE. Loss of Pointer (LOP) is set when a valid
pointer value has not been found within eight consecutive
frames. This register bit is cleared when a valid pointer is found
for three consecutive frames. Path Alarm Indication Signal
(PAIS) (Reg30H, bit 3) is set when the H1 and H2 bytes are
set to all ones for 3 consecutive frames. This register bit is
cleared when a valid pointer is found for three consecutive
frames. PAIS does not cause LOP to be set. The SPE location
is provided to the Receive ATM Cell Processor for cell extrac-
tion.
The BIP−8 value calculated over the previous SPE is com-
pared with the B3 byte of the current path overhead. Up to
65,535 errors can be detected per second. Errors are recorded
in a 16-bit saturating counter that can be read through the
controller interface.
Path Far End Block Errors (PFEBE) are detected by examining
the value in bits 1 through 4 of G1. This value (0−8h) is added
to the count in a 16-bit saturating counter that can be read
through the controller interface.
Path Far End Receive Failures (PFERF) are detected by ex-
amining the value in bits 1 through 4 of G1. If this value is 9h
for two consecutive frames, PFERF is set. This register bit is
cleared when anything other than 9h appears for two consec-
utive frames.
Path Remote Defect Indication (Path RDI) is detected by ex-
amining bit 5 of G1. If this value is 1h for 5 consecutive frames,
PYEL is set. This register bit is cleared when a 0 appears in
bit 5 for 5 consecutive frames.
Receive ATM Cell Processor (RACP)
The RACP block provides cell delineation, HEC checking and
correcting, cell filtering for idle/unassigned cells, cell payload
descrambling, status indications, and error monitoring.
Cell delineation is performed by comparing the HEC sequence
calculated over the first four bytes of the SPE to the fifth byte.
If these values match, cell boundary has been determined. If
not, the calculation advances one byte further into the payload
(bytes 2−5) and the check is performed again. The HEC se-
quence is a CRC−8 calculated over the first 4 octets of the ATM
cell header using the polynomial x8 + x2 + x + 1. The coset x6
+ x4 + x2 + 1 is added (modulo 2) to the residue before com-
parison with the received sequence. This is the HUNT state of
the cell delineation process. When a valid match has occurred
the process enters the PRESYNC state. When 7 consecutive
matches occur the process enters the SYNC state. If 6 con-
secutive incorrect HEC matches are detected the process
moves back to the HUNT state. The average time for cell de-
lineation is 93µs for STS−1 and 31µs for STS−3C.
The HEC sequence is used not only to check for cell align-
ment, but also to insure that integrity of the ATM header. The
HEC is used to correct single bit errors and to detect multiple
bit errors. This feature can be disabled. The register file con-
tains two saturating 8-bit counters for HEC errors; one for cells
with single bit errors and another for multiple-bit errors. Cells
with multiple bit errors are optionally discarded. Figure 3
shows the state diagram for HEC.
The RACP optionally discards Idle/Unassigned cells. These
cells contain a VPI/VCI address of 0h. Also, a Header Mask
and Header Match register are provided to allow cells with a
particular header characteristic in GFC, PTI and CLP to be
filtered.
The payload of valid cells are descrambled using the polyno-
mial x43 +1. The cell headers are not descrambled since they
11
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