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PDF CY7C9537B Data sheet ( Hoja de datos )
| Número de pieza | CY7C9537B | |
| Descripción | OC-48/STM-16 Framer-POSIC2G | |
| Fabricantes | Cypress Semiconductor | |
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CONFIDENTIAL
CY7C9537B
OC-48/STM-16 Framer–POSIC2G™
Features
• OC-48/STS-48/STM-16, OC-12/STS-12/STM-4,
OC-3/STS3/STM-1 rates, concatenated and non-concat-
enated
— Complies with ITU-Standards G.707/Y.1322 and
G.783[1,2]
— Complies with Bellcore GR253 rev.1, 1997[3]
www.DataSheet4U—.coCmhannelized operation: supports 16xSTS-3c/VC4,
4xSTS-12c/VC4-4c, 2xSTS-24c/VC4-8c, and
1xSTS-48c/VC4-16c within OC-48 stream
— Supports TUG3 mapping in SDH mode
• Full duplex mapping of ATM cells over SONET/SDH
— Complies with ITU-Standards I.432.2[4,5,6]
• Full duplex mapping of packet-over-SONET/SDH: IETF
RFC 1619/1662/2615 (HDLC/PPP)[7,8,9]
• Generic Protocol Encapsulator/Decapsulator delin-
eates packets/frames with length-CRC frame construct
— Generic Framing Procedure (GFP) per ANSI
T1X1.5[10,11,12]
— GFP 268r1
— Simple Data Link (SDL) - IETF RFC2823 [13]
— Cypress Hybrid Data Transport (HDT) [14]
• User-programmable encapsulation
• User-programmable clear channel transport
• User-programmable SONET/SDH bypass
• Programmable frame tagging engine for packet
preclassification enables such features as
— MPLS label lookup and tagging
— PPP: LCP and NCP tagging
— PPP control packets optionally sent to host CPU
interface
— MAC/layer 3 address look up and tagging
• Programmable A1A2 processing bypass in Rx direction
with frame sync input
• Complete section overhead (SOH), line overhead
(LOH), and path overhead (POH) processing
• APS extraction, CPU interrupt generation, and
programmable insertion of APS byte
• Line side APS port interface
• Provision for protection switching on SONET/SDH port
• Programmable PRBS generator and receiver
• Serial port to access line/section data communication
channel (DCC) and voice communication channel
(VCC)
• Full duplex UTOPIA/OIF-SPI (POS-PHY) level 3 interface
[15,16]
• 16-bit/32-bit host CPU interface bus
• JTAG and boundary scan
• Glue-less interface with Cypress CYS25G0101DX
OC-48 PHY
• 0.18-µm CMOS, 504-pin BGA package
• +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for
HSTL/LVPECL I/O supply, and +0.75V/2.0V reference
Applications
• Multiservice nodes
• ATM switches and routers
• Packet routers
• Multi-service routers
• SONET/SDH add-drop mux for packet/data applications
• SONET/SDH/ATM/POS test equipment
Notes:
1. ITU-T Recommendation G.707. “Network Node Interface for the Synchronous Digital Hierarchy.” 1996.
2. ITU-T Recommendation G.783. “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.” 2000.
3. Bellcore Publication GR-253-Core. “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.” 1997.
4. ITU-T Recommendation I.432.3. “B-ISDN User-Network Interface—Physical Layer Specification: 1544 kbit/s and 2048 kbit/s operation.” 1999.
5. American National Standards Institute. “Synchronous Optical Network (SONET)—Basic Description including Multiplex Structure, Rates and Formats.” ANSI
T1.105–1995.
6. American National Standards Institute. “Synchronous Optical Network (SONET)—Payload Mappings.” ANSI T1.105.02–1998.
7. Simpson, W. “PPP Over SONET/SDH.” RFC 1619. May 1994.
8. Simpson, W., ed. “PPP in HDLC-like Framing.” RFC 1662. Daydreamer. July 1994.
9. Malis, A. and Simpson, W. “PPP Over SONET/SDH.” RFC 2615. June 1999.
10. Hernandez-Valencia, E. Lucent Technologies. “A Generic Frame Format for Data Over SONET (DoS).” March 2000.
11. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999.
12. Hernandez-Valencia, E. Lucent Technologies. T1X1.5/2000-209. “Generic Framing Procedure (GFP) Specification.” October 9–13, 2000.
13. Carlson, J., P. Langner, E.J. Hernandez-Valencia, and J. Manchester. “PPP over Simple Data Link (SDL) using SONET/SDH with ATM-like Framing.” rfc2823.txt,
May 2000.
14. Pankaj, K. “A Hybrid Data Transport Protocol for Optical Networks.” RFC draft-jha-optical-hdt-00.txt. November 2000.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02079 Rev. *F
Revised May 3, 2005
1 page  
CONFIDENTIAL
CY7C9537B
Programmable Frame Tagging Engine
The Programmable Frame Tagging Engine provides preclas-
sification of the packets/frames at the wire rate. This helps in
utilizing the link layer device more efficiently.
The Programmable Frame Tagging Engine enables the user
to perform preclassification of all the incoming packets into
one of the 16 possible categories. Since each channel can
have up to 16 different categories, and up to 16 concatenated
channels are possible, this engine supports up to 256 different
categories. For classification, two-pass comparison can be
specified. For each comparison a field of up to six bytes can
be selected within the first 64 bytes of the packet and
compared with up to 16 programmed values. The comparison
www.DataSheeti4sUo.ncoambit by bit basis and any bit comparison can be masked
with a user programmable mask register. A four-bit tag is
attached to the cell/packet, based on the match. Host CPU can
program these parameters through register programming.
The following functions can be achieved with the help of the
Programmable Frame Tagging Engine:
• Incoming packet analysis to parse packets/frames/cells at
wire speed.
• User-programmable routing of control packets to CPU for
processing.
• Incoming frames tagged based on bits (such as congestion)
in incoming packets.
• User-programmable offset to locate Ethernet and other
frames within DOS and other proprietary M.AN networking
protocols to allow MPLS processing.
SONET/SDH Bypass
POSIC2G supports the SONET/SDH framer/deframer bypass
mode. Host CPU can program such bypass. In this mode, the
data frames/packets, encapsulated by one of the encapsu-
lators, will be transmitted transparently through SONET/SDH
blocks to the fiber side and vice versa.
System Memory at
Host System
Control Packets
Data
Packets
Packets not
belonging to this
Node
Tag #0
Data
Tag #1
Data
Tag #2
Tagging enables sorting of packets by
Host System
POSIC
Data
SONET/SDH
........
Tag #n
Data
TTL-expired and
other discard
packets
Tag #13
Data
Errored packets
(CRC and Parity)
Node-sourced
packets to be
sinked
Tag #14
Data
Tag #15
Data
Figure 3. Frame Tagging Engine Data Sorting Diagram
Document #: 38-02079 Rev. *F
Page 5 of 43
5 Page 
CONFIDENTIAL
CY7C9537B
Pin Description (continued)
Signal Name
RDAT[31:0]
I/O Pad Type
O LVTTL
www.DataSheet4U.com
RADD[7:0]
O LVTTL
RMOD[1:0]
O LVTTL
RPRTY
O LVTTL
Pins JTAG
Description
32 N
POS:
Receive Packet Data Bus (RDAT[31:0])
The RDAT[31:0] bus carries the packet octets that are read from the
receive FIFO and the in-band port address of the selected receive
FIFO. RDAT[31:0] is considered valid only when RVAL is asserted.
Given the defined data structure, bit 31 is received first and bit 0 is
received last.
ATM:
Receive Cell Data Bus (RxData[31:0])
The RDAT[31:0] bus carries the cell octets that are read from the
receive FIFO. RDAT[31:0] is considered valid only when RENB is
asserted. Given the defined data structure, bit 31 is received first and
bit 0 is received last
RDAT[31:0] is updated on the rising edge of RCLK. This bus is
big-endian in format.
HBST:
Receive Data Bus (RDATA[31:0])
32-bit Data Bus, the data is valid when RDVAL signal is active.
8N
HBST:
Receive Port Address (RADDR[7:0]).
When RDVAL signal is active, this address on this bus indicates port
address in RADDR[3:0] and tag value in RADDR[7:4]. In
single-channel mode all 8 bits will contain the tag value. RADDR is
considered valid only when RDVAL is asserted
2N
POS:
Receive Word Modulo (RMOD[1:0]) signal.
RMOD[1:0] indicates the number of valid bytes of data in RDAT[31:0].
The RMOD bus should always be all zero, except during the last
double-word transfer of a packet on RDAT[31:0]. When REOP is
asserted, the number of valid packet data bytes on RDAT[31:0] is
specified by RMOD[1:0]
RMOD[1:0] = “00” RDAT[31:0] valid
RMOD[1:0] = “01” RDAT[31:8] valid
RMOD[1:0] = “10” RDAT[31:16] valid
RMOD[1:0] = “11” RDAT[31:24] valid
RMOD[1:0] is considered valid only when RVAL is asserted.
HBST:
Receive Data Byte Valid (RBVAL[1:0]) signals.
This indicates the number of bytes data bytes valid on the RDATA bus,
00 = 4 bytes valid, 11 = 1 byte valid.
1N
POS:
Receive Parity (RPRTY) signal.
The receive parity (RPRTY) signal indicates the parity calculated over
the RDAT bus. RPRTY supports both odd and even parity.
ATM:
Receive Parity (RxPrty) signal.
Data bus odd parity.
HBST:
Receive Bus Parity (RPARITY) signal.
Receive bus parity, Even/Odd parity calculated on the data bus alone
or on all the bus signals (RDATA, RADDR, RDVAL, RBVAL, RSOP,
REOP, RERR).
Document #: 38-02079 Rev. *F
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