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PDF CY7C9536B Data sheet ( Hoja de datos )
| Número de pieza | CY7C9536B | |
| Descripción | OC-48/STM-16 Framer | |
| Fabricantes | Cypress Semiconductor | |
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CONFIDENTIAL
CY7C9536B
OC-48/STM-16 Framer with VC - POSIC2GVC™
Features
• OC-48/STS-48/STM-16, OC-12/STS-12/STM-4,
OC-3/STS3/STM-1 rates, concatenated and non-concat-
enated
• Complies with ITU-Standards G.707/Y.1322 and
G.783[1,2]
www.DataSheet•4UC.coommplies with Bellcore GR253 rev.1, 1997[3]
• Channelized operation: supports 16xOC-3 and 4xOC-12
within OC-48 stream
• Supports TUG3 mapping in SDH mode
• Virtual concatenation enables secure and dedicated
bandwidth provisioning[4]
• Up to 16 channels
• From 50-Mbps to 1.2-Gbps bandwidth per channel
• STS-1 and STS-3c granularity
• Full duplex mapping of ATM cells over SONET/SDH
• Complies with ITU-Standards I 432.2[5,6,7]
• Full duplex mapping of packet-over-SONET/SDH: IETF
RFC 1619/1662/2615 (HDLC/PPP)[8,9,10]
• Generic Framing Procedure (GFP) per ANSI
T1X1.5[11,12,13] Protocol Encapsulator/Decapsulator
delineates GFP frames with length-CRC frame
construct
• GFP 268r1
• User-programmable encapsulation
• User-programmable clear channel transport
• User-programmable SONET/SDH bypass
• Programmable frame tagging engine for packet
preclassification enables such features as
• MPLS label lookup and tagging
• PPP: LCP and NCP tagging
• PPP control packets optionally sent to host CPU
interface
• MAC/layer 3 address look up and tagging.
• Programmable A1A2 processing bypass in Rx direction
with frame sync input
• Complete section overhead (SOH), line overhead
(LOH), and path overhead (POH) processing
• APS extraction, CPU interrupt generation, and
programmable insertion of APS byte
• Line side APS port interface
• Provision for protection switching on SONET/SDH port
• Programmable PRBS generator and receiver
• Serial port to access line/section data communication
channel (DCC) and voice communication channel
(VCC)
• Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3
interface[14,15]
• 16-bit/32-bit host CPU interface bus
• JTAG and boundary scan
• Glueless interface with Cypress CYS25G0101DX
OC-48 PHY
• 0.18-um CMOS, 504-pin BGA package
• +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for
HSTL/LVPECL I/O supply, and +0.75V/2.0V reference
Applications
• Multi-service nodes
• ATM switches and routers
• Packet routers and multiservice routers
• SONET/SDH/Add-Drop Mux for packet/data applications
• SONET/SDH/ATM/POS test equipment
Notes:
1. ITU-T Recommendation G.707. “Network Node Interface for the Synchronous Digital Hierarchy.” 1996.
2. ITU-T Recommendation G.783. “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.” 2000.
3. Bellcore Publication GR-253-Core. “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.” 1997.
4. Jones, N., Lucent Microelectronics, and C. Murton, Nortel Networks. “Extending PPP over SONET/DSH with Virtual Concatenation, High-Order and Low-Order
payloads.” Internet Draft. June 2000.
5. ITU-T Recommendation I.432.3. “B-ISDN User-Network Interface—Physical Layer Specification: 1544 kbit/s and 2048 kbit/s Operation.” 1999.
6. American National Standards Institute. “Synchronous Optical Network (SONET)—Basic Description Including Multiplex Structure, Rates and Formats.” ANSI
T1.105-1995.
7. American National Standards Institute. “Synchronous Optical Network (SONET)—Payload Mappings.” ANSI T1.105.02–1998.
8. Simpson, W. “PPP over SONET/SDH.” RFC 1619. May 1994.
9. Simpson, W., ed. “PPP in HDLC-like Framing,” RFC 1662. Daydreamer. July 1994.
10. Malis, A. and W. Simpson. “PPP over SONET/SDH,” RFC 2615. June 1999.
11. Hernandez-Valencia, E., Lucent Technologies. “A Generic Frame Format for Data over SONET (DoS).” March 2000.
12. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999.
13. Hernandez-Valencia, E., Lucent Technologies. T1X1.5/2000-209. “Generic Framing Procedure (GFP) Specification.” October 9–13, 2000.
14. ATM Forum, Technical Committee. UUTOPIA 3 Physical Layer Interface.” Af-phy-0136.000. November 1999.
15. Can, R. and R. Tuck. “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link-Layer Devices.” OIF-SPI3-01.0. June 2000.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02078 Rev. *G
Revised April 25, 2005
1 page  
CONFIDENTIAL
CH P1aGckbetE(Gthiegranbeitt)
1
1Gb
CH Packet
2 (Gigabit
Ethernet)
SPI - 3
Link
Layer
P
O
S
I
C
www.DataSheet4U.com
300Mb
CH (3x100 Mb
3 Ethernet
OR TDM in
clear channel
mode)
SONET
Cloud
CY7C9536B
SPI - 3
P
O
S Link
I Layer
C
1Gb
Packet
CH
1
1Gb
Packet CH
(Gigabit 2
Ethernet)
300Mb
(3x100 Mb
Ethernet
OR TDM in
clear channel
mode)
CH
3
16
CH 15
1n
3
2
1
SONET
CH Cloud
3
CH
2
15
2
CH
1
n
16
3
1
CH
3
CH
2
(OC3 SPEs may arrive in different order.
At receiveing end, POSIC stores the SPEs in
external memory to re-arrange them in correct order.)
Figure 2. Explanation of Virtual Concatenation
Generic Frame Encapsulation/Decapsulation
POSIC2GVC supports a variety of protocols/packets/frames
to transport over a SONET/SDH link. For clarity of reference,
in this document, framing of packets/cells into these protocols
is called “encapsulation,” and the engine performing encapsu-
lation is called an “encapsulator.” Similarly, deframing is called
“decapsulation,” and the engine performing decapsulation is
called a “decapsulator.”
Three different encapsulator and decapsulator engines are
integrated into POSIC2GVC.
The ATM encapsulator computes and adds the HEC field,
scrambles the cells and passes on to the VC block. In case of
underflow, ATM encapsulator also creates programmable idle
cells.
The ATM decapsulator checks for HEC and integrity of the cell.
It descrambles the cells, isolates and discards idle cells and
passes ATM cells to the Programmable Frame Tagging
Engine.
HDLC encapsulator performs Asynchronous Control
Character Mapping (ACCM), stuffing, flag sequence insertion
and scrambling. Optionally, up to 16 bytes of header is inserted
ahead of the packet while framing the packet. The host CPU
can program this 16-byte header through register programing.
Such programmable header insertion enables encapsulation
of PPP, frame relay or other protocol.
The HDLC decapsulator descrambles the incoming byte
stream and searches the flag sequence. Upon finding the
boundary, decapsulator performs destuffing and ACCM
demapping before passing the packets to the Programmable
Frame Tagging Engine.
The Generic Framing Procedure (GFP) Encapsulator/Decap-
sulator supports delineation based on length-CRC pair header
construct. In the transmit direction, it computes a 16-bit header
CRC based on 2-byte length value received from the link layer
device. The length and CRC fields are inserted as header of
the frame ahead of the packet. Scrambling of the payload and
32-bit payload CRC computation and insertion are optional.
Document #: 38-02078 Rev. *G
Page 5 of 46
5 Page 
CONFIDENTIAL
CY7C9536B
Pin Description
Signal Name I/O Pad Type Pins JTAG
Pin Description
Line Interface Signals
RXFRAME_PULSE I HSTL/LVTTL 1
/LVPECL
N
Optional frame pulse input for line interface. Active HIGH.
TXFRAME_PULSE O HSTL/LVTTL 1 N
Frame pulse output for line interface. Active HIGH.
RXD[31:0]
I HSTL/LVTTL 32 N
/LVPECL
32-bit single ended receive data bus for SONET/SDH link. This bus
can be configured as two 16-bit buses in APS operation.
RXCLK
I HSTL/LVTTL 1
/LVPECL
N
Receive clock input from the PHY device for line interface.
RXCLKs
www.DataSheet4U.com
TXCLKOUT
I HSTL/LVTTL
/LVPECL
O HSTL/LVTTL
1
1
N
N
Receive clock input from the Slave PHY device for SONET/SDH
link to support APS.
Transmit Clock to physical layer device for line interface. This will
be RXCLK or the TXCLKI based on the clock selection in the SONET
Tx block register. During loopback this is same as the RXCLK.
TXCLKI
I HSTL/LVTTL 1
/LVPECL
N
Input transmit clock from physical layer device for line interface.
TXD[31:0]
O HSTL/LVTTL 32 N
32-bit single ended transmit data bus for line interface. This bus
can be configured as two 16-bit buses in APS operation.
SONETTX_PAROU O HSTL/LVTTL 1
T
N
SONET Tx Parity Output. Can be ODD/EVEN parity, as programmed
in the SONET/SDH Tx block register.
SONETRX_PARIN
I HSTL/LVTTL 1
/LVPECL
N
SONET Rx Parity Input. Can be ODD/EVEN parity, as programmed
in the SONET/SDH Rx block register.
LFI_n
I LVTTL
1Y
Line fault indicator.
When LOW, this signal indicates that the PHY has detected Loss of
Optical signal on the SONET/SDH link.
Overhead Bytes Access—Serial Ports
Clk2MHz
O LVTTL
1Y
TOH Serial Port Clock Output. TOHDout is clocked out on rising
edge of this clock and TOHDin is latched-in with falling edge of this
clock. The frequency is 2.048 MHz, derived from SysClk.
Clk16MHz
O LVTTL
1Y
POH Serial Port Clock Output. POHDout is clocked out on rising
edge of this clock and POHDin is latched-in with falling edge of this
clock. The frequency is 16.625 MHz, derived from SysClk
TE1STROBE
O LVTTL
1Y
Transmit E1 Strobe. Transmit TOH serial port data start indication.
Active HIGH pulse generated once in every 125 ms. Indicates the first
bit of E1 Byte.
TE2STROBE
O LVTTL
1Y
Transmit E2 Strobe. Active HIGH pulse generated once in every
125 ms. Indicates the first bit of E2 Byte.
TPOHSTART
O LVTTL
1Y
Transmit POH Serial Port Data Start Indication. Active HIGH pulse
generated once in every 125 ms.
TOHSDIN
I LVTTL
1Y
Transport over head serial port data input.
POHSDIN
I LVTTL
1Y
Path over head serial port data input.
RE1STROBE
O LVTTL
1Y
Receive E1 Strobe. Receive TOH serial port data start indication.
Active HIGH pulse generated once in every 125 ms. Indicates that the
POSIC2GVC expects the first bit of the first byte of E1 should
accompany the next clock edge. MSB is transmitted first.
RE2STROBE
O LVTTL
1Y
Receive E2 Strobe. Active HIGH pulse generated once in every 125
ms. Indicates that the POSIC2GVC expects the first bit of the first byte
of E2 should accompany the next clock edge. MSB is transmitted first.
RPOHSTART
O LVTTL
1Y
Receive POH Serial Port Data Start Indication. Active HIGH pulse
generated once in every 125 ms. Indicates that the POSIC2GVC
expects the first bit of the first byte of RPOH should accompany the
next clock edge.
TOHSDOUT
O LVTTL
1Y
Transport over head serial port data output.
Document #: 38-02078 Rev. *G
Page 11 of 46
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