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PDF CY28324 Data sheet ( Hoja de datos )
| Número de pieza | CY28324 | |
| Descripción | FTG for Intel Pentium 4 CPU and Chipsets | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY28324 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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PRELIMINARY
CY28324
FTG for Intel® Pentium® 4 CPU and Chipsets
Features
• Compatible to Intel® CK-00, CK-Titan & CK-408 Clock
Synthesizer/Driver Specifications
• System frequency synthesizer for Intel 850, Brookdale
(845) and Brookdale - G Pentium® 4 Chipsets
• Programmable clock output frequency with less than 1
MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when Watchdog Timer
time-out
• Capable of generating system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength support
• Programmable output skew support
• Power management control inputs
• Available in 48-pin SSOP
CPU 3V66 PCI REF 48M 24_48M
x 2 x 4 x 10 x 2 x 1 x 1
Block Diagram
X1
X2
*FS0:4
VTT_PWRGD#
*CPU_STP#
*MULTSEL0:1
XTAL
OSC
PLL Ref Freq
PLL 1
Divider
Network
Stop
Clock
Control
PWR_DWN#
*PCI_STP#
PLL2
SDATA
SCLK
SMBus
Logic
Stop
Clock
Control
2
VDD_REF
REF0:1
Pin Configuration
SSOP-48
*MULTSEL1/REF1
VDD_CPU
CPU0:1, CPU0:1#
VDD_REF
X1
X2
GND_PCI
*FS2/PCI_F0
VDD_MREF
*FS3/PCI_F1
3VMREF, 3VMREF# *MODE/PCI_F2
VDD_PCI
VDD_3V66
*FS4/PCI0
3V66_0:3
PCI1
PCI2
VDD_PCI
PCI_F0:2
GND_PCI
PCI3
PCI4
PCI0:6
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RST#
GND_48MHz
*FS0/48MHz
VDD_48MHz
48MHz
*FS1/24_48MHz
VDD_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF0/MULTSEL0*
47 GND_REF
46 VDD_MREF
45 3VMREF/CPU_STP#*
44 3VMREF#/PCI_STP#*
43 GND_MREF
42 PWR_DWN#
41 CPU0
40 CPU0#
39 VDD_CPU
38 CPU1
37 CPU1#
36 GND_CPU
35 IREF
34 VDD_CORE
33 GND_CORE
32 VDD_3V66
31 3V66_0
30 3V66_1
29 GND_3V66
28 3V66_2
27 3V66_3
26 SCLK
25 SDATA
24_48MHz
Note:
1. Signals marked with ‘*’ have internal pull-up resistor.
RST#
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07002 Rev. *A
Revised November 14, 2001
1 page  
PRELIMINARY
CY28324
Swing Select Functions
MULTSEL1 MULTSEL0
00
Board Target
Trace/Term Z
50Ω
00
60Ω
01
50Ω
01
60Ω
10
50Ω
10
60Ω
11
50Ω
11
60Ω
00
50Ω
00
60Ω
01
50Ω
01
60Ω
10
50Ω
10
60Ω
11
50Ω
11
60Ω
Reference R,
IREF = VDD/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Output
Current
IOH = 4*IREF
IOH = 4*IREF
IOH = 5*IREF
IOH = 5*IREF
IOH = 6*IREF
IOH = 6*IREF
IOH = 7*IREF
IOH = 7*IREF
IOH = 4*IREF
IOH = 4*IREF
IOH = 5*IREF
IOH = 5*IREF
IOH = 6*IREF
IOH = 6*IREF
IOH = 7*IREF
IOH = 7*IREF
VOH @ Z
1.0V @ 50
1.2V @ 60
1.25V @ 50
1.5V @ 60
1.5V @ 50
1.8V @ 60
1.75V @ 50
2.1V @ 60
0.47V @ 50
0.56V @ 60
0.58V @ 50
0.7V @ 60
0.7V @ 50
0.84V @ 60
0.81V @ 50
0.97V @ 60
Document #: 38-07002 Rev. *A
Page 5 of 23
5 Page 
PRELIMINARY
Data Byte 10
Bit
Bit 7
Bit 6
Bit 5
Pin#
10
7
6
Name
CPU_Skew2
CPU_Skew1
CPU_Skew0
Bit 4
Bit 3
Bit 2
23 Reserved
22 PCI_Skew1
-- PCI_Skew0
Bit 1
Bit 0
-- 3V66_Skew1
-- 3V66_Skew0
Pin Description
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
3v66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
CY28324
Power-On
Default
0
0
0
0
0
0
0
0
Data Byte 11
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
--
--
--
--
--
--
--
--
Name
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
Pin Description
If ROCV_FREQ_SEL is set, the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be
use to determine the recovery CPU output frequency
when a Watchdog Timer time-out occurs.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When FS_Override
bit is cleared, the same frequency ratio stated in the
Latched FS[4:0] register will be used. When it is set, the
frequency ratio stated in the SEL[4:0] register will be used.
Power-On
Default
0
0
0
0
0
0
0
0
Data Byte 12
Bit
Bit 7
Pin#
Name
-- ROCV_FREQ_SEL
Pin Description
ROCV_FREQ_SEL determines the source of the recover
frequency when a Watchdog Timer time-out occurs. The
clock generator will automatically switch to the recovery
CPU frequency based on the selection on
ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] &
ROCV_FREQ_M[6:0]
Power-On
Default
0
Document #: 38-07002 Rev. *A
Page 11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CY28324.PDF ] | |
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