PDF CY28322-2 Data sheet ( Hoja de datos )

Número de pieza	CY28322-2
Descripción	133 Mhz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
Fabricantes	Cypress
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No Preview Available ! PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Benefits Supports next generation Pentium processors using differential clock drivers • Multiple output clocks at different frequencies Motherboard clock generator — Two pairs of differential CPU outputs, up to 200 MHz — Support multiple CPUs and a chipset — Nine synchronous PCI clocks, three free-running — Support for PCI slots and chipset — Six 3V66 clocks — Supports AGP, DRCG reference, and Hub Link — Two 48-MHz clocks — Supports USB host and graphic controllers — One reference clock at 14.318 MHz — Supports ISA slots and I/O chip — One VCH clock • Spread Spectrum clocking (down spread) Enables reduction of EMI and overall system cost • Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) Enables ACPI-compliant designs • Two select inputs (Mode select & IC Frequency Select) Supports up to four CPU clock frequencies • 48-pin TSSOP package Widely available, standard package enables lower cost Logic Block Diagram X1 XTAL X2 OSC PWR PLL Ref Freq PLL 1 S1:2 PWR_GD# CPU_STOP# Gate Divider Network PWR Stop Clock Control PCI_STOP# PWR_DWN# PWR /2 PWR Stop Clock Control PWR PLL 2 PWR VDD_REF REF VDD_CPU CPU1:2 CPU#1:2 VDD_PCI PCI_F0:2 PCI0:5 VDD_3V66 3V66_0:1 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN VDD_48MHz USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 Pin Configurations TSSOP Top View XTAL_IN XTAL_OUT GND_REF PCI_F0 PCI_F1 PCI_F2 GND_PCI PCI0 PCI1 PCI2 VDD_PCI PCI3 PCI4 PCI5 VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PWR_DWN# VDD_CORE GND_CORE PWR_GD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_REF REF0 S1 CPU_STOP# VDD_CPU CPU1 CPU#1 GND_CPU VDD_CPU CPU2 CPU#2 IREF S2 USB DOT VDD_48 MHz GND_48 MHz 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA SDATA SCLK SMBus Logic Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07145 Rev. B Revised December 14, 2002 1 page PRELIMINARY CY28322-2 Data Byte 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 34 35 6 Name DOT USB PCI_F2 5 PCI_F1 4 PCI_F0 6 PCI_F2 5 PCI_F1 4 PCI_F0 Pin Description DOT 48-MHz Output Enable USB 48-MHz Output Enable Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# PCI_F2 Output Enable PCI_F1Output Enable PCI_F0 Output Enable Type R/W R/W R/W Power-on Default 1 1 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 Data Byte 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name – TBD – TBD 29 3V66_0 31 3V66_1/VCH 20 66IN/3V66_5 19 66BUFF2 18 66BUFF1 17 66BUFF0 Pin Description N/A N/A 3V66_0 Output Enable 1 = Enabled; 0 = Disabled 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled 3V66_5 Output Enable 1 = Enable; 0 = Disable Note. This bit should be used when pin 24 is configured as 3v66_5 output. Do not clear this bit when pin 24 is configured as 66IN input. 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled Type R R R/W R/W R/W R/W R/W R/W Power-on Default 0 0 1 1 1 1 1 1 Data Byte 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name N/A N/A 66BUFF [2:0] 66BUFF [2:0] DOT DOT USB USB Pin Description N/A N/A Tpd 66IN to 66BUFF propagation delay control DOT edge rate control USB edge rate control Type R R R/W R/W R/W R/W R/W R/W Power-on Default 0 0 0 0 0 0 0 0 Byte 6: Vendor ID Bit 7 Bit 6 Bit 5 Bit Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Type R R R Power-on Default 0 0 0 Document #: 38-07145 Rev. B Page 5 of 17 5 Page Switching Waveforms (continued) PCI-PCI Clock Skew PCI PRELIMINARY PCI 3V66-PCI Clock Skew 3V66 t6 PCI t7 CPU Clock Cycle-Cycle Jitter Host_b Host t8A t8B Cycle-Cycle Clock Jitter t9A t9B CLK CY28322-2 Document #: 38-07145 Rev. *B Page 11 of 17 11 Page

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