PDF CY2291 Data sheet ( Hoja de datos )

Número de pieza	CY2291
Descripción	Three-PLL General Purpose EPROM Programmable Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Features ■ Three integrated phase-locked loops ■ EPROM programmability ■ Factory-programmable (CY2291) or field-programmable (CY2291F) device options ■ Low-skew, low-jitter, high-accuracy outputs ■ Power-management options (Shutdown, OE, Suspend) ■ Frequency select option ■ Smooth slewing on CPUCLK ■ Configurable 3.3 V or 5 V operation ■ 20-pin SOIC Package Functional Description The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock synchoronous systems. All parts provide a highly configurable set of close for PC motherboard applications. Each of four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2291 can be configured for either 5 V or 3.3 V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10 MHz to 25 MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHZ to 30 MHz can be used. Customers using the 32 kHz oscillator must connect a 10-MW resistor in parallel with the 32 kHz crystal. Part Number Outputs Input Frequency Range CY2291 8 10 MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) CY2291I 8 10 MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) CY2291F 8 10 MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) CY2291FI 8 10 MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) Output Frequency Range 76.923 kHz – 100 MHz (5 V) 76.923 kHz – 80 MHz (3.3 V) 76.923 kHz – 90 MHz (5 V) 76.923 kHz – 66.6 MHz (3.3 V) 76.923 kHz – 90 MHz (5 V) 76.923 kHz – 66.6 MHz (3.3 V) 76.923 kHz – 80 MHz (5 V) 76.923 kHz – 60.0 MHz (3.3 V) Specifics Factory programmable Commercial temperature Factory programmable Industrial temperature Field programmable Commercial temperature Field programmable Industrial temperature Logic Block Diagram 32XIN 32XOUT XTALIN XTALOUT S0 S1 S2/SUSPEND OSC. OSC. CPLL (8 BIT) UPLL (10 BIT) SPLL (8 BIT) /1,2,4 /1,2,4,8 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 /2,3,4 32K XBUF CPUCLK CLKA CLKB CLKC CLKD CLKF SHUTDOWN/ OE CONFIG EPROM Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-07189 Rev. F • San Jose, CA 95134-1709 • 408-943-2600 Revised December 1, 2011 1 page CY2291 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Supply voltage .............................................–0.5 V to + 7.0 V DC input voltage ..........................................–0.5 V to + 7.0 V Storage temperature ................................ –65 °C to +150 °C Operating Conditions[5] Maximum soldering temperature (10 sec) .................. 260 °C Junction temperature.................................................. 150 °C Package power dissipation....................................... 750 mW Static discharge voltage.............................................≥ 2000 V (per MIL-STD-883, Method 3015) Parameter Description Part Numbers VDD VDD VBATT[4] TA Supply voltage, 5.0 V operation Supply voltage, 3.3 V operation Battery backup voltage Commercial operating temperature, ambient Industrial operating temperature, ambient All All All CY2291/CY2291F CY2291I/CY2291FI CLOAD CLOAD fREF Max. load capacitance 5.0 V operation Max. load capacitance 3.3 V operation External reference crystal External reference clock[6, 7, 8] All All All All tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min 4.5 3.0 2.0 0 −40 − − 10.0 1 0.05 Max Unit 5.5 V 3.6 V 5.5 V +70 °C +85 °C 25 pF 15 pF 25.0 MHz 30 MHz 50 ms Electrical Characteristics, Commercial 5.0 V Parameter Description Conditions VOH VOL VOH–32 HIGH-level output voltage LOW-level output voltage 32.768-kHz HIGH-level output voltage IOH = 4.0 mA IOL = 4.0 mA IOH = 0.5 mA VOL–32 32.768-kHz LOW-level output voltage IOL = 0.5 mA VIH HIGH-level input voltage[9] Except crystal pins VIL LOW-level input voltage[9] Except crystal pins IIH Input HIGH current VIN = VDD – 0.5 V IIL Input LOW current VIN = +0.5 V IOZ Output leakage current Three-state outputs IDD VcoDmDmsueprcpilayl[c1u0]rrent VDD = VDD Max., 5 V operation IDDS IBATT VshDuDtdpoowwnermsoudpep[l1y0c] urrent in Shutdown active, excluding VBATT VBATT power supply current VBATT = 3.0 V CY2291/CY2291F Min 2.4 − VBATT 0.5 − 2.0 − − − − − − − Typ − − − − − − <1 <1 75 10 5 Max − 0.4 − 0.4 − 0.8 10 10 250 100 50 15 Unit V V V V V V μA μA μA mA μA μA Notes 5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to Whitepaper “Crystal Parameters Recommendation for Cypress Frequency Synthesizers” for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150Ω pull up resistor to VDD be connected to the Xout pin. 9. Xtal inputs have CMOS thresholds. 10. Load = Max., VIN = 0V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06•(FCPLL+FUPLL+2•FSPLL)+0.27•(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF+FXBUF). Document Number: 38-07189 Rev. F Page 5 of 16 5 Page Switching Waveforms Figure 2. All Outputs, Duty Cycle and Rise/Fall Time t1 t2 OUTPUT t3 t4 Figure 3. Output Three-State Timing [3] OE ALL THREE-STATE OUTPUTS CLK OUTPUT RELATED CLK SELECT CPU t5 t6 Figure 4. CLK Outputs Jitter and Skew t9A t7 Figure 5. CPU Frequency Change OLD SELECT Fold NEW SELECT STABLE t8 & t10 Fnew Test Circuit VDD 0.1 μF VDD 0.1 μF OUTPUTS GND CLK out CLOAD CY2291 Document Number: 38-07189 Rev. *F Page 11 of 16 11 Page

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