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PDF CY2292 Data sheet ( Hoja de datos )
| Número de pieza | CY2292 | |
| Descripción | Three-PLL General-Purpose EPROM-Programmable Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2292
Three-PLL General-Purpose
EPROM-Programmable Clock Generator
Three-PLL General-Purpose EPROM-Programmable Clock Generator
Features
Benefits
■ Three integrated phase locked loops (PLLs)
■ Erasable programmable read only memory (EPROM)
programmability
■ Factory programmable (CY2292) or field programmable
(CY2292F) device options
■ Low-skew, low-jitter, high accuracy outputs
■ Power management options (shutdown, OE, suspend)
■ Frequency select option
■ Smooth slewing on CPUCLK
■ Configurable 3.3 V or 5 V operation
■ 16-pin small-outline integrated circuit (SOIC) package
(CY2292F also in TSSOP)
■ Generates up to three custom frequencies from one external
source
■ Easy customization and fast turnaround
■ Programming support available for all opportunities
■ Supports low power applications
■ Eight user selectable frequencies on CPU PLL
■ Allows downstream PLLs to stay locked on CPUCLK output
■ Industry standard packaging saves on board space
Functional Description
For a complete list of related documentation, click here.
Selector Guide
Part Number
Input Frequency Range
Output Frequency Range
Specifics
CY2292SC, SL, SXC, SXL 10 MHz to 25 MHz (external crystal) 76.923 kHz to 100 MHz (5 V) Factory programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 80 MHz (3.3 V) Commercial temperature
CY2292SI, SXI
10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V) Factory programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Industrial temperature
CY2292F, FXC, FZX
10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V) Field programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Commercial temperature
CY2292FXI, FZXI
10 MHz to 25 MHz (external crystal) 76.923 kHz to 80 MHz (5 V) Field programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 60.0 MHz (3.3 V) Industrial temperature
Logic Block Diagram
XTALIN
XTALOUT
S0
S1
S2 / SUSPEND
OSC.
CPLL
( 8 BIT)
UPLL
( 10 BIT)
SPLL
( 8 BIT)
/1,2,4
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96, 104
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
SHUTDOWN / OE
CONFIG
EPROM
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07449 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 26, 2016
1 page  
CY2292
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage .............................................–0.5 V to +7.0 V
DC input voltage ..........................................–0.5 V to +7.0 V
Storage temperature ................................ –65 C to +150 C
Maximum soldering temperature (10 sec) ................. 260 C
Junction temperature ................................................. 150 C
Package power dissipation ...................................... 750 mW
Static discharge voltage
(per MIL-STD-883, method 3015) 2000 V
Operating Conditions
Parameter [5]
Description
Part Numbers
VDD Supply voltage, 5.0 V operation All
VDD Supply voltage, 3.3 V operation All
TA
Commercial operating
CY2292 / CY2292F
temperature, ambient
Industrial operating temperature, CY2292I / CY2292FI
ambient
CLOAD
Maximum load capacitance 5.0 V All
operation
CLOAD
Maximum load capacitance 3.3 V All
operation
fREF
External reference crystal
All
External reference clock [6, 7, 8] All
Min Max Unit
4.5 5.5 V
3.0 3.6 V
0 70 C
40 85 C
– 25 pF
– 15 pF
10.0 25.0 MHz
1 30 MHz
Notes
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD / 2.
7. Refer to white paper “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended
that a 150 pull up resistor to VDD be connected to the Xout pin.
Document Number: 38-07449 Rev. *L
Page 5 of 19
5 Page 
CY2292
Switching Characteristics
Industrial, 5.0 V
Parameter
Name
t1 Output period
Description
Clock output range, CY2292SI, SXI
5 V operation
CY2292FXI, FZXI
Output duty cycle[21]
Duty cycle for outputs, defined as t2 t1[22]
fOUT > 66 MHz
Duty cycle for outputs, defined as t2 t1[22]
fOUT < 66 MHz
t3 Rise time
Output clock rise time[23]
t4 Fall time
Output clock fall time[23]
t5
Output disable time
Time for output to enter tristate mode after
SHUTDOWN/OE goes LOW
t6
Output enable time
Time for output to leave tristate mode after
SHUTDOWN/OE goes HIGH
t7 Skew
Skew delay between any identical or related
outputs[22, 24]
t8
CPUCLK slew
Frequency transition rate
t9A
Clock jitter[24]
Peak-to-peak period jitter (t9A max – t9A min),
percentage of clock period (fOUT < 4 MHz)
t9B
Clock jitter[24]
Peak-to-peak period jitter (t9B max – t9B min)
(4 MHz < fOUT < 16 MHz)
t9C
Clock jitter[28]
Peak-to-peak period jitter (16 MHz < fOUT < 50
MHz)
t9D
Clock jitter[28]
Peak-to-peak period jitter (fOUT > 50 MHz)
t10A
Lock time for CPLL
Lock time from power-up
t10B Lock time for UPLL and Lock time from power-up
SPLL
Slew limits
CPU PLL slew limits CY2292SI, SXI
CY2292FXI, FZXI
Min
11.1
(90 MHz)
12.5
(80 MHz)
40
45
–
–
–
–
–
1.0
–
–
–
–
–
–
20
20
Typ Max Unit
–
13000
ns
(76.923 kHz)
–
13000
ns
(76.923 kHz)
50 60 %
50 55 %
3 5 ns
2.5 4 ns
10 15 ns
10 15 ns
< 0.25
0.5
ns
–
< 0.5
20.0 MHz /
ms
1%
< 0.7
1
ns
< 400
500
ps
< 250
< 25
< 0.25
350
50
1
ps
ms
ms
– 90 MHz
– 80 MHz
Notes
21. XBUF duty cycle depends on XTALIN duty cycle.
22. Measured at 1.4 V.
23. Measured between 0.4 V and 2.4 V.
24. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit.
Document Number: 38-07449 Rev. *L
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY2292.PDF ] | |
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