|
|
PDF HSP50214B Data sheet ( Hoja de datos )
| Número de pieza | HSP50214B | |
| Descripción | Programmable Downconverter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HSP50214B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
TM
Data Sheet
HSP50214B
May 2000 File Number 4450.3
Programmable Downconverter
[ /Title
(HSP5
0214B)
/Sub-
ject
(Pro-
gram-
mable
Down-
con-
verter)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Down-
con-
verter,
Down
Con-
verter,
Pro-
gram-
mable
Down-
con-
verter,
DSP,
AMPS,
TDMA
, North
Ameri-
can
TDMA
, GSM,
The HSP50214B Programmable Downconverter converts
digitized IF data into filtered baseband data which can be
processed by a standard DSP microprocessor. The
Programmable Downconverter (PDC) performs down
conversion, decimation, narrowband low pass filtering, gain
scaling, resampling, and Cartesian to Polar coordinate
conversion.
The 14-bit sampled IF input is down converted to baseband
by digital mixers and a quadrature NCO, as shown in the
Block Diagram. A decimating (4 to 32) fifth order Cascaded
Integrator-Comb (CIC) filter can be applied to the data
before it is processed by up to 5 decimate-by-2 halfband
filters. The halfband filters are followed by a 255-tap
programmable FIR filter. The output data from the
programmable FIR filter is scaled by a digital AGC before
being re-sampled in a polyphase FIR filter. The output
section can provide seven types of data: Cartesian (I, Q),
polar (R, θ), filtered frequency (dθ/dt), Timing Error (TE), and
AGC level in either parallel or serial format.
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
HSP50214BVC
0 to 70 120 Ld MQFP
HSP50214BVI
-40 to 85 120 Ld MQFP
PKG. NO.
Q120.28x28
Q120.28x28
Block Diagram
C(7:0)
IN(13:0)
GAIN
ADJ
(2:0)
COF
SOF
CLKIN
PROCCLK
REFCLK
MICROPROCESSOR
READ/WRITE
CONTROL
LEVEL DETECT
5TH
ORDER
CIC
FILTER
CARRIER
NCO
5TH
ORDER
CIC
FILTER
RESAMPLING
NCO
Features
• Up to 65 MSPS Front-End Processing Rates (CLKIN) and
55MHz Back-End Processing Rates (PROCCLK)
Clocks May Be Asynchronous
• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to ≅12.94 MSPS with Output
Bandwidths to ≅ 982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and
Carrier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and
Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to
Optimize Output Signal Resolution; Fixed or Auto Gain
Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator
for AFC Loops and Demodulation of AM, FM, FSK, and
DPSK
• Input Level Detector for External I.F. AGC Support
Applications
• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
• Compatible with HSP50210 Digital Costas Loop for PSK
Reception
• Evaluation Platform Available
AGC LOOP FILTER
AGC
POLYPHASE
FIR AND
HALFBAND
FILTERS
POLYPHASE
FIR AND
HALFBAND
FILTERS
I OUT
CARTESIAN
TO
POLAR
COORDINATE
CONVERTER
MAG.
PHASE
Q OUT
FREQ
DISCRIMINATOR
TIMING ERROR
∆
SEROUTA
SEROUTB
AOUT(15:0)
BOUT(15:0)
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HSP50214B
Pin Descriptions
NAME
VCC
GND
CLKIN
TYPE
-
-
I
IN(13:0)
I
ENI I
GAINADJ(2:0)
I
PROCCLK
I
AGCGNSEL
COF
I
I
COFSYNC
I
SOF
I
SOFSYNC
I
AOUT(15:0)
O
BOUT(15:0)
O
DESCRIPTION
Positive Power Supply Voltage.
Ground.
Input Clock. This clock should be a multiple of the input sample rate. All input section processing occurs on the rising
edge of CLKIN. The frequency of CLKIN is designated fCLKIN.
Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the MSB (see Control
Word 0).
Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or interpolated (see Con-
trol Word 0). In gated mode, one sample is taken per CLKIN when ENI is asserted. The input sample rate is desig-
nated fS, which can be different from fCLKIN when ENI is used.
GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added to the shift
code from the microprocessor (µP) interface. The shift code is saturated to a maximum code of F. The gain is offset
by (6dB)(GAINADJ); (000 = 0dB gain adjust; 111 = 42dB gain adjust) GAINADJ2 is the MSB. See “Using the Input
Gain Adjust Control Signals” Section.
Processing Clock. PROCCLK is the clock for all processing functions following the CIC Section. Processing is per-
formed on PROCCLK’s rising edge. All output timing is derived from this clock.
NOTE: This clock may be asynchronous to CLKIN.
AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative to PROCCLK.
Gain setting 1 is selected when AGCGNSEL = 1.
Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the Carrier NCO
(see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold times are relative to CLKIN.
This input is compatible with the output of the HSP50210 Costas loop [1].
Carrier Offset Frequency Sync. This signal is asserted one CLK before the most significant bit (MSB) of the offset
frequency word (see Serial Interface Section). The setup and hold times are relative to CLKIN. This input is com-
patible with the output of the HSP50210 Costas loop [1].
Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the Re-Sampler
NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold times are relative
to PROCCLK. This input is compatible with the output of the HSP50210 Costas loop [1].
Re-Sampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset frequency word
(see Serial Interface Section). The setup and hold times are relative to PROCCLK. This input is compatible with the
output of the HSP50210 Costas loop [1].
Parallel Output Bus A. Two parallel output modes are available on the HSP50214B. The first is called the Direct Out-
put Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes
directly from the Output MUX Section (see Output Control Section). The most significant byte of AOUT always out-
puts the most significant byte of the Parallel Direct Output Port whose data type is selected via µP interface.
AOUT15 is the MSB. In this mode, the AOUT(15:0) bus is updated as soon as data is available. DATARDY is as-
serted to indicate new data. For this mode, the output choices are: I, |r|, or f. The format is 2’s complement, except
for magnitude, which is unsigned binary with a zero as the MSB.
The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a
FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase, and frequency informa-
tion; a data type is selected using SEL(2:0). Up to 7 data sets are stored in the Buffer RAM Output Port. The LSBytes
of the AOUT and BOUT busses form the 16 bits for the buffered output mode and can be used for buffered mode
while the MSBytes are outputting data in the direct output mode. For this mode, the output formats are the same as
the Direct Output Port mode.
Parallel Output Bus B. Two parallel output modes are available on the HSP50214B. The first is called the Direct Out-
put Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes
directly from the Output MUX Section (see Output Control Section). The most significant byte of BOUT always out-
puts the most significant byte of the Parallel Direct Output Port whose data type is selected via µP interface.
BOUT15 is the MSB. In this mode, the BOUT(15:0) bus is updated as soon as data is available. DATARDY is as-
serted to indicate new data. For this mode, the output choices are: Q, φ, or |r|. The format is 2’s complement, except
for magnitude which is unsigned binary with a zero as the MSB.
The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a
FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude, phase, and frequency informa-
tion; a particular information is selected using SEL(2:0). Up to 7 data sets is stored in the Buffer RAM Output Port.
The least significant byte of BOUT can be used to either output the least significant byte of the B Parallel Direct
Output Port or the least significant byte of the Buffer RAM Output Port. See Output Section. For this mode the output
formats are the same as the Direct Output Port mode.
3-5
5 Page 
HSP50214B
See Figures 4-7 for an interpolated input example, detailing
the associated spectral results.
Interpolation Example:
The specifications for the interpolated input example are:
CLKIN = 40MHz
Input Sample Rate = 5 MSPS
PROCCLK = 28MHz
Interpolate by 8, Decimate by 10
Desired 85dB dynamic range output bandwidth = 500kHz
Input Level Detector
The Input Level Detector Section measures the average
magnitude error at the PDC input for the microprocessor by
comparing the input level against a programmable
threshold and then integrating the result. It is intended to
provide a gain error for use in an AGC loop with either the
RF/IF or A/D converter stages (see Figure 8). The AGC
loop includes Input Level Detector, the microprocessor and
an external gain control amplifier (or attenuator). The input
samples are rectified and added to a threshold
programmed via the microprocessor interface, as shown in
Figure 9. The bit weighting of the data path through the
input threshold detector is shown in Figure 10. The
threshold is a signed number, so it should be set to the
inverse of the desired input level. The threshold can be set
to zero if the average input level is desired instead of the
error. The sum of the threshold and the absolute value of
the input is accumulated in a 32-bit accumulator. The
accumulator can handle up to 218 samples without
overflow. The integration time is controlled by an 18-bit
counter. The integration counter preload (ICPrel) is
programmed via the microprocessor interface through
Control Word 1. Only the upper 16 bits are programmable.
The 2 LSBs are always zero. Control Word 1, Bits 29-14
are programmed to:
ICPrel = (N) ⁄ 4 + 1
(EQ. 1)
where N is the desired integration period, defined as the
number of input samples to be integrated. N must be a
multiple of 4: [0, 4, 8, 12, 16 .... , 218].
IN(13:0)
INPUT
FORMAT †
GAINADJ(2:0)
INPUT LEVEL DETECTOR †
STATUS (0) †
LEVEL
DETECT
INPUT_THRESH †
INTG_MODE †
INTG_INTEVAL †
14 15
14 15
18
18
NCO † †
4
EN
DELAY 3
LIMIT
3
∑
BYPASS †
ENI
CONTROL WORD 0
CONTROL WORD 1
CLKIN
INTERP †
DELAY 3
4
CONTROL
LOGIC
INPUT_MODE †
INPUT_FMT †
INPUT_THRESH †
INTG_MODE †
INTG_INTEVAL †
† Controlled via microprocessor interface.
†† See NCO Section for more details.
FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION
BYPASS
PROCCLK = 28MHz
5MHz
CIC
FILTER
MIN. R = 4
CLKIN = 5MHz
HB/FIR FILTER
MAX. fS = 4MHz
(EXCEEDED IN
BYPASS PATH)
500kHz = 85dB
BANDWIDTH
(NOT ACHIEVED
WITH CIC FILTER
PATH)
Without Interpolation, the CIC bypass path exceeds the HB/FIR filter
input sample rate and the CIC filter path will not yield the desired
85dB dynamic range band width of 500kHz.
FIGURE 4. STATEMENT OF THE PROBLEM
↑8 (0 STUFF) = 40MHz
4MHz
5MHz
CIC FILTER
R = ↓10
CLKIN = 40MHz
HB/FIR FILTER
500kHz = 85dB
BANDWIDTH
FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION
APPROACH
3-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HSP50214B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HSP50214A | Programmable Downconverter | Intersil Corporation |
| HSP50214AVC | Programmable Downconverter | Intersil Corporation |
| HSP50214AVI | Programmable Downconverter | Intersil Corporation |
| HSP50214B | Programmable Downconverter | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |