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PDF AD9888 Data sheet ( Hoja de datos )
| Número de pieza | AD9888 | |
| Descripción | Analog Flat Panel Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
170 MSPS maximum conversion rate
500 MHz programmable analog bandwidth
0.5 V to 1.0 V analog input range
Less than 450 ps p-p PLL clock jitter at 170 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
2:1 analog input mux
4:2:2 output format mode
Midscale clamping
Power-down mode
Low power: <1 W typical at 170 MSPS
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
GENERAL DESCRIPTION
The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 170 MSPS encode rate
capability and full-power analog bandwidth of 500 MHz supports
resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface that has a 170 MHz triple ADC with
an internal 1.25 V reference phase-locked loop (PLL) to generate a
pixel clock from HSYNC and COAST; midscale clamping; and
programmable gain, offset, and clamp controls. The user provides
only a 3.3 V power supply, analog input, and HSYNC and COAST
signals. Three-state CMOS outputs can be powered from 2.5 V
to 3.3 V.
The on-chip PLL of the AD9888 generates a pixel clock from the
HSYNC and COAST inputs. Pixel clock output frequencies
100 MSPS/140 MSPS/170 MSPS
Analog Flat Panel Interface
AD9888
RAIN0
RAIN1
GAIN0
GAIN1
BAIN0
BAIN1
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
COAST
CLAMP
CKINV
CKEXT
FILT
SCL
SDA
A0
FUNCTIONAL BLOCK DIAGRAM
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
CLAMP
CLAMP
CLAMP
ADC 8
ADC 8
ADC 8
8
8
8
8
8
8
2
SYNC
PROCESSING
AND CLOCK
GENERATION
REF
DRA[7:0]
DRB[7:0]
DGA[7:0]
DGB[7:0]
DBA[7:0]
DBB[7:0]
DATACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
SERIAL REGISTER
AND
POWER MANAGEMENT
AD9888
Figure 1.
range from 10 MHz to 170 MHz. PLL clock jitter is typically
less than 450 ps p-p at 170 MSPS. When the COAST signal is
presented, the PLL maintains its output frequency in the absence of
HSYNC. A sampling phase adjustment is provided. Data, HSYNC,
and clock output phase relationships are maintained. The PLL
can be disabled, and an external clock input can be provided as
the pixel clock. The AD9888 also offers full sync processing for
composite sync and sync-on-green applications.
A CLAMP signal is generated internally or can be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a 2-wire serial port.
Fabricated in an advanced CMOS process, the AD9888 is
provided in a space-saving, 128-lead, MQFP, surface-mount,
plastic package and is specified over the 0°C to 70°C temperature
range. The AD9888 is also available in a Pb-free package.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD9888
Data Sheet
SPECIFICATIONS
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Temperature Coefficient
Input Bias Current
Input Capacitance
Input Resistance
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock to Data Skew (tskew)
I2C Timing2
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter3
Sampling Phase Temperature
Coefficient
Temp
Test
Level
AD9888KSZ-100/-1401
Min Typ
8
Max
AD9888KSZ-170
Min Typ
8
Max
Unit
Bits
25°C I
Full VI
25°C I
Full VI
25°C I
±0.5 ±1.25/−1.0
+1.35/−1.0
±0.5 ±2.0
±2.5
Guaranteed
±0.6 +1.25/−1.0
+1.50/−1.0
±0.75
±2.25
±2.75
Guaranteed
LSB
LSB
LSB
LSB
25°C I
25°C I
25°C V
25°C IV
Full IV
Full V
Full IV
Full VI
Full VI
Full VI
Full VI
Full V
Full VI
Full IV
Full IV
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full IV
Full VI
Full IV
25°C IV
Full IV
Full IV
1.0
100
3
1
7
2.5
44 49
1.20 1.25
±50
100/140
−1.25
4.7
4.0
250
4.7
4.0
250
4.7
4.0
15
100/140
470
15
0.5
1
2
90
9.0
53
1.30
10
+1.25
110
10
700
1000
1.0
100
3
1
7
2.5
44 49
1.20 1.25
±50
170
−1.25
4.7
4.0
250
4.7
4.0
250
4.7
4.0
15
170
450
15
0.5
1
2
90
9.0
53
1.30
10
+1.25
110
10
700
1000
V p-p
V p-p
ppm/°C
μA
μA
pF
M
mV
% FS
% FS
V
ppm/°C
MSPS
MSPS
ns
μs
μs
ns
μs
μs
ns
μs
μs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
Rev. C | Page 4 of 36
5 Page 
AD9888
Data Sheet
Mnemonic
Outputs
DRA[7:0]
DRB[7:0]
DGA[7:0]
DGB[7:0]
DBA[7:0]
DBB[7:0]
DATACK,
DATACK
HSOUT
VSOUT
SOGOUT
REF BYPASS
RMIDSCV
BMIDSCV
FILT
Power Supply
VD
VDD
PVD
Description
Data Output, Red Channel, Port A.
Data Output, Red Channel, Port B.
Data Output, Green Channel, Port A.
Data Output, Green Channel, Port B.
Data Output, Blue Channel, Port A.
Data Output, Blue Channel, Port B.
Each channel has two ports. When the part is operated in single-channel mode (channel mode bit (Register 0x15, Bit 7) = 0),
all data is presented to Port A, and Port B is placed in a high impedance state. Programming the channel mode bit to 1
establishes dual-channel mode, where pixels are alternately presented to Port A and Port B of each channel. These appear
simultaneously; two pixels are presented at the time of every second input pixel when the output mode bit (Register 0x15,
Bit 6) is set to 1 (parallel mode). When the output mode bit is set to 0, pixel data appear alternately on the two ports, one
new sample with each incoming pixel (interleaved mode). In dual-channel mode, the first pixel after HSYNC is routed to
Port A. The second pixel goes to Port B, the third to Port A, and so on. This can be reversed by setting the A/B invert control bit
(Register 0x15, Bit 5) to 1. The delay from the pixel sampling time to the output is fixed. When the sampling time is changed by
adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The DATACK, DATACK,
and HSOUT outputs are also moved; therefore, the timing relationship among the signals is maintained.
Data Output Clock, Data Output Clock Complement.
These are differential data clock output signals to be used to strobe the output data and HSOUT into external logic. They
are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9888 is
operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. When operated in dual-
channel mode, the clock frequency is half the pixel frequency, as is the output data frequency. When the sampling time is
changed by adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The data,
DATACK, DATACK, and HSOUT outputs are all moved; therefore, the timing relationship among the signals is maintained.
Either or both signals can be used, depending on the timing mode and interface design used.
Horizontal Sync Output.
This is a reconstructed, phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be
programmed via serial bus registers. By maintaining alignment with DATACK, DATACK, and data, data timing with respect
to horizontal sync can always be determined.
Verical Sync Output.
Sync-on-Green (SOG) Slicer Output.
This pin can be programmed to output either the sync-on-green slicer comparator or an unprocessed but delayed version
of the HSYNC input. See the sync processing block diagram (Figure 27) to view how this pin is connected. Note that other
than slicing off SOG, the output from this pin receives no other additional processing on the AD9888. VSYNC separation is
performed via the sync separator.
Internal Reference Bypass.
The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most
AD9888 applications. If higher accuracy is required, an external reference can be employed instead.
Red Channel Midscale Voltage Bypass.
Blue Channel Midscale Voltage Bypass.
These bypasses for the internal midscale voltage references should each be connected to ground through 0.1 μF capacitors.
The exact voltage varies with the gain setting of the blue channel.
External Filter Connection. For proper operation, the internal PLL that generates the pixel clock requires an external filter.
Connect the filter shown in Figure 9 to this pin. For optimal performance, minimize noise and parasitics on this node.
Main Power Supply. These pins supply power to the main elements of the circuit. This supply should be as quiet and
filtered as possible.
Digital Output Power Supply.
A large number of output pins (up to 52) switching at high speed (up to 110 MHz) generates significant power supply
transients (noise). These supply pins are identified separately from the VD pins; therefore, special care must be taken to
minimize output noise transferred into the sensitive analog circuitry. If the AD9888 is interfacing with lower voltage logic,
VDD can be connected to a lower supply voltage (as low as 2.5 V) for compatibility.
Clock Generator Power Supply.
The most sensitive portion of the AD9888 is the clock generation circuitry. These pins provide power to the PLL generated pixel
clock and help the user design for optimal performance. The designer should provide noise-free power to these pins.
Rev. C | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9888.PDF ] | |
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