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PDF ASCELL3912 Data sheet ( Hoja de datos )
| Número de pieza | ASCELL3912 | |
| Descripción | ISM 868 MHz/ 433 MHz and 315 MHz FSK Transmitter | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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ASCell3912
ISM 868 MHz, 433 MHz and 315 MHz
FSK Receiver Cell
Preliminary Data Sheet
1 page  
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Austria Mikro Systeme International AG
1.2 Digital Controller
The principal function of the digital controller is demodulation, bit synchronization and the detec-
tion of the received data protocol, according to the definition of transmitted bits. Furthermore, a
first syntax check and plausibility check of detected data is provided. A data protocol received
completely is put into a receive buffer, where a micro controller (µC) can read it out via a serial
interface.
The receiver can be externally configured with several operation parameters, LNA gain setting,
used frequency band, and timing constant for the watch dog timer. The serial interface also al-
lows to configure the digital controller by the µC.
The receiver writes the state information into a status register. This status information can be
read out from the µC out of the status register of the receiver.
1.2.1 Microprocessor Clock
The microprocessor clock frequency FCLK is generated by dividing the XTAL frequency FXOSC by
4 if XO-SEL is ´H´ and by dividing the XTAL frequency FXOSC by 6 if XO-SEL is ´L´.
Note: XO-SEL and RF-SEL are internal generated signals from the FB[1:0] bits of the setup information.
1.2.2 ASCell3912 Digital Part Timing
In Figure 2 the timing of a complete receive sequence can be seen. Transmission starts at an
arbitrary point in time. First the crystal oscillator is switched on. A minimum time of 5 ms is al-
lowed for the frequency to settle to the final value. Then the receiver executes a wake-up se-
quence consisting of 6 wake-up bursts. The wake-up bursts are unequally spaced to guarantee
interference free detection of an ongoing transmission also in the presence of burst interferers.
During a wake-up burst the receiver scans for an active transmission on the air interface. The
wake-up sequence is optimized to combat GSM and CT2 type interferers.
After an ongoing transmission has been detected the receiver goes to receiving mode, the
WAKE_UP line goes high, and reception of data starts. Depending on the number of interferers
present, reception of all data may take up to 3 data blocks. As soon as all data has been de-
tected successfully, the RE_INT pin issues a positive pulse, to indicate the availability of data,
and the internal data ready flag (DR) in the ASCell3912 state register is set. The RE_INT line
may be used to trigger a interrupt procedure, which is executed at the availability of data. When
data is read out by the micro controller the internal data ready flag (DR) in the RX-status register
is cleared and it is only set, when a complete data sequence has received again. No further
pulse is issued on the RE_INT line, but the micro controller has to poll for new data during an
ongoing reception. If transmission stops, the WAKE_UP line goes low and a pulse is issued on
the RE_INT line to indicate the termination of transmission at CMT.
In Figure 2 also the timing where the microprocessor clock (µC_CLK) is active is shown. The
clock is active with the start of the detection phase of the SC3911. The clock is shut down 16
clock cycles (TCAI) after the falling edge of the second interrupt on the RE_INT pin.
Rev. A, February 2000
Page 5 of 14
5 Page 
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Austria Mikro Systeme International AG
2.5 Digital Pin Characteristics
TAMB = 23 °C, VDD = 3.6 V, unless specified otherwise. GND is the 0 V reference.
Symbol Parameter
Conditions
Min Typ Max
µC_CLK (µC clock output)
VOH High level output voltage IOH =-1 mA
VDD-0.5
-
VOL Low level output voltage IOL =1 mA
- 0.3
tr Rise time
CLoad = 10 pF
20
td Fall time
CLoad = 10 pF
20
jcc Cycle to cycle jitter
+/-5
DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)
VIH High level input voltage
VDD-0.5
-
VIL Low level input voltage
- 0.3
IIH High level input current VIH= VDD
1
IIL Low level input current VIL =0 V
-1
FD_CLK D_CLK frequency
3
RE_INT (interrupt output); WAKEUP (µC wakeup output)
VOH High level output voltage IOH = -1mA
VDD-0.5
-
VOL Low level output voltage IOL = 1mA
- 0.3
Units
V
V
ns
ns
%
V
V
µA
µA
kHz
V
V
3 Pin-out Information
Note: pin numbers have arbitrary ordering and numbering - will be defined during design
Pin Name
1 RF+
2 RF-
3 LC+
4 LC-
5 XTAL+
6 XTAL-
7 AVDD
8 AGND
9 GMC
10 RFGND
11 DGND
12 TEST1
13 TEST2
14 uC_CLK
15 RE_INT
16 WAKEUP
Type
I
I
I/O
I/O
I
O
P
P
I/O
I
P
I/O
I/O
O
O
O
Description
LNA input
LNA input
LNA tank
LNA tank
XTAL oscillator input
XTAL oscillator output
Analog positive supply
Analog negative supply
Base-Band Low Pass frequency set
RF GND
Digital negative supply
pin for test purposes
pin for test purposes
Clock output for micro controller
Interrupt at first received data block and receive end
Micro controller wake up; high during ongoing reception
Rev. A, February 2000
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ASCELL3912.PDF ] | |
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