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PDF ASCELL3911 Data sheet ( Hoja de datos )
| Número de pieza | ASCELL3911 | |
| Descripción | ISM 868 MHz/ 433 MHz and 315 MHz FSK Transmitter | |
| Fabricantes | austriamicrosystems AG | |
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ASCell3911
ISM 868 MHz, 433 MHz and 315 MHz
FSK Transmitter
Preliminary Data Sheet
1 page  
ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet
ASCell3911
Austria Mikro Systeme International AG
1.4.1 Duty-Cycle Operation
In certain countries, it is required to reduce the average transmit power but it is allowed to keep
the peak power high. Therefore a duty-cycled operation mode is implemented in the ASCell3911.
By selecting this operation mode, the duty cycle of the transmit signal is set to 50%, related to an
observation interval of 10 ms. This function is be implemented in the burst interference resistant
protocol encoder. The duty cycle operation is set via the bit duty cycle operation (DCO).
Note: DCO is one bit of the control information.
1.4.2 Transmission Modi
The ASCell3911 supports two different transmission modii:
• The event oriented Single Message Transmission (SMT) where four times alternate syn-
chronization and data packets are transmitted. Due to the limited transmission time this
mode needs less power than CMT but supports no direct information about the duration of a
transmitted command. The bit SMT/CMT is “L” for this mode.
• The status oriented Continuous Message Transmission (CMT) where alternate synchroniza-
tion and data packets are transmitted as long as one button is pressed. This mode is less
power efficient than SMT but the duration of a command can be directly transported by the
duration of the transmission power. The bit SMT/CMT is “H” for this mode.
Note: SMT/CMT is one bit of the control information.
1.5 Driving Amplifier
The driving amplifier has a differential open collector output optimized for driving of small, sym-
metrical high-impedance loop antennas. The amplifier drives a nominal RF current of 1 mARMS.
The maximal differential voltage swing is about 2,8 VPP. Therefore, the output power is a function
of the connected load impedance. With a 2 kΩ differential load a nominal peak output power (to
the antenna) of ≈2 mW is obtained. Please note that the finally radiated power (from antenna) is
lower and strongly dependent on the efficiency (function of the size) of the antenna to be used.
1.6 µC Interface and Power Management
The ASCell3911 contains a direct interface to a micro controller (µC). The µC interface of the
ASCell3911 consists of the following five pins:
”Transmit data input” (DATA).
“Active ”H” transmit data enable” (D_EN).
”Transmit data clock input” (D_CLK).
”Active ”L” µC reset output/transmitter wakeup end input” (WAKEUP).
”µC clock output/active ”L” start-up input” (µC_CLK).
These lines support the µC with the required reset and clock signals and control the ASCell3911
internal power on/off circuit, which wakes up and shuts down the whole transmitter consisting of
the ASCell3911 and the µC.
Figure 3 shows a typical interconnection of the ASCell3911 with a typical µC. Figure 4 presents
a related timing for power up and down of the transmitter.
Rev. A, February 2000
Page 5 of 13
5 Page 
ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet
ASCell3911
Austria Mikro Systeme International AG
DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)
VIH High level input voltage
VDD-0,5
-
VIL Low level input voltage
- 0,3
IIH High level input current VIH= VDD
1
IIL Low level input current VIL =0 V
-1
WAKEUP (µC clear output / transmitter power down input)
VOH High level output voltage IOH = -1mA
VDD-0,5
-
VOL Low level output voltage IOL = 1mA
- 0,3
VIH High level input voltage
VDD-0,5
-
VIL Low level input voltage
- 0,3
IIH High level input current VIH = VDD
1
IIL Low level input current VIL =0 V; Due to
internal pull-up
-40
V
V
µA
µA
V
V
V
V
µA
µA
2.4.1 µController Interface
Symbol Parameter
Conditions / Notes
Tbit FSK Data Bit duration
Twe Time between Wake up and Data Data input prepared to
Enable
receive data
Ted Time between Data Enable and Data input prepared to
Data
receive data
Tde Time between Data and Data Start-up and lock PLL
Enable
Tet Time between Data Enable and Start-up and lock PLL
Transmit
Twt Time between Wake up and
Transmit start
Tca Time that CLK output stays ac-
tive after Twt
VPOR
Power-On-Reset threshold volt- RESET invalid when Vdd <
age VCCminPOR
TPOR Power-On-Reset duration
VCCminPOR Minimum Supply Voltage for valid
Power-On-Reset output
Min
tbd
tbd
tbd
tbd
1,6
2
Typ Max Units
tbd s
s
s
s
s
tbd s
tbd s
1,8 V
10 ms
1,2 V
3 Pin Description
Note: pin ordering is preliminary - will be fixed at fab-in.
Pin Name
1 RF+
2 RF-
3 PAGND
Type
A
A
P
Description
Power amplifier output (open collector)
Power amplifier output (open collector)
Power amplifier ground
Rev. A, February 2000
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ASCELL3911.PDF ] | |
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