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PDF AT45DB642 Data sheet ( Hoja de datos )
| Número de pieza | AT45DB642 | |
| Descripción | 64-megabit 2.7-volt Only Dual-interface DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Dual-interface Architecture
– Dedicated Serial Interface (SPI Modes 0 and 3 Compatible)
– Dedicated Parallel I/O Interface (Optional Use)
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 8192 Pages (1056 Bytes/Page) Main Memory
• Supports Page and Block Erase Operations
• Two 1056-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• 20 MHz Maximum Clock Frequency – Serial Interface
• 5 MHz Maximum Clock Frequency – Parallel Interface
• Hardware Data Protection
• Commercial and Industrial Temperature Ranges
Description
The AT45DB642 is a 2.7-volt only, dual-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications. The
dual-interface of the AT45DB642 allows a dedicated serial interface to be connected to a
DSP and a dedicated parallel interface to be connected to a microcontroller or vice versa.
Pin Configurations
Pin Name
CS
SCK/CLK
SI
SO
I/O7 - I/O0
WP
RESET
RDY/BUSY
SER/PAR
Function
Chip Select
Serial Clock/Clock
Serial Input
Serial Output
Parallel Input/Output
Hardware Page Write Protect Pin
Chip Reset
Ready/Busy
Serial/Parallel Interface Control
DataFlash Card(1)
TSOP Top View
Type 1
NC
NC
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK/CLK
SI*
SO*
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 NC
38 NC
37 NC
36 NC
35 I/O7*
34 I/O6*
33 I/O5*
32 I/O4*
31 VCCP*
30 GNDP*
29 I/O3*
28 I/O2*
27 I/O1*
26 I/O0*
25 SER/PAR*
24 NC
23 NC
22 NC
21 NC
Note:
*Optional Use – See pin description
text for connection information.
7654321
64-megabit
2.7-volt Only
Dual-interface
DataFlash®
AT45DB642
Note: 1. See AT45DCB008 Datasheet.
Rev. 1638F–DFLSH–09/02
1
1 page  
1638F–DFLSH–09/02
AT45DB642
As with the Continuous Array Read, the CS pin must remain low during the loading of the
opcode, the address bytes, the don't care bytes, and the reading of data. During a Burst Array
Read with Synchronous Delay, when the end of a page in main memory is reached (the last bit
or the last byte of the page has been clocked out), the system must send an additional 32
don't care clock cycles before the first bit (or byte if using the parallel interface mode) of the
next page can be read out. These 32 don't care clock cycles are necessary to allow the device
enough time to cross over the burst read boundary (the crossover from the end of one page to
the beginning of the next page). By utilizing the 32 don't care clock cycles, the system does
not need to delay the SCK/CLK signal to the device which allows synchronous operation when
reading multiple pages of the memory array. Please see the detailed read timing waveforms
for illustrations (beginning on page 21) on which clock cycle data will actually begin to be
output.
When the last bit (or byte in the parallel interface mode) in the main memory array has been
read, the device will continue reading back at the beginning of the first page of memory. The
transition from the last bit (or byte when using the parallel interface) of the array back to the
beginning of the array is also considered a burst read boundary. Therefore, the system must
send 32 don't care clock cycles before the first bit (or byte if using the parallel interface mode)
of the memory array can be read.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Burst Array Read
with Synchronous Delay is defined by the fBARSD specification. The Burst Array Read with Syn-
chronous Delay bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory page read allows the user to read data
directly from any one of the 8192 pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H
or D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and a series of don’t care bytes (four don’t care bytes
if using the serial interface or 60 don’t care bytes if the using parallel interface). The first 13
bits (PA12 - PA0) of the 24-bit (three-byte) address sequence specify the page in main mem-
ory to be read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the
starting byte address within that page. The four or 60 don’t care bytes that follow the three
address bytes are sent to initialize the read operation. Following the don’t care bytes, addi-
tional pulses on SCK/CLK result in data being output on either the SO (serial output) pin or the
parallel output pins (I/O7 - I/O0). The CS pin must remain low during the loading of the
opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a
page in main memory is reached, the device will continue reading back at the beginning of the
same page. A low-to-high transition on the CS pin will terminate the read operation and tri-
state the output pins (SO or I/O7 - I/O0).
BUFFER READ: Data can be read from either one of the two buffers, using different opcodes
to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer
1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a buffer read,
the opcode must be clocked into the device followed by three address bytes comprised of 13
don’t care bits and 11 buffer address bits (BFA10 - BFA0). Following the three address bytes,
an additional don’t care byte must be clocked in to initialize the read operation. Since the
buffer size is 1056 bytes, 11 buffer address bits are required to specify the first byte of data to
be read from the buffer. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is
reached, the device will continue reading back at the beginning of the buffer. A low-to-high
transition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O0).
5
5 Page 
AT45DB642
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset condition
as long as a low level is present on the RESET pin. Normal operation can resume once the
RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. The RESET pin is also internally pulled high; there-
fore, in low pin count applications, connection of the RESET pin is not necessary if this pin and
feature will not be utilized. However, it is recommended that the RESET pin be driven high
externally whenever possible.
READY/BUSY: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through an external
pull-up resistor), will be pulled low during programming/erase operations, compare operations,
and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
PARALLEL PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are
used to supply power for the parallel input/output pins (I/O7-I/O0). The VCCP and GNDP pins
need to be used if the parallel port is to be utilized; however, these pins should be treated as
“don’t connects” if the SER/PAR pin is not connected or if the SER/PAR pin is always driven
high externally.
Power-on/Reset
State
When power is first applied to the device, or when recovering from a reset condition, the
device will default to SPI Mode 3 or Inactive Clock Polarity High. In addition, the output pins
(SO or I/O7 - I/O0) will be in a high impedance state, and a high-to-low transition on the CS pin
will be required to start a valid instruction. The SPI mode or the clock polarity mode will be
automatically selected on every falling edge of CS by sampling the inactive Clock State.
System
Considerations
The SPI interface is controlled by the serial clock SCK, serial input SI and chip select CS pins.
The sequential 8-bit parallel interface is controlled by the clock CLK, 8 I/Os and chip select CS
pins. These signals must rise and fall monotonically and be free from noise. Excessive noise
or ringing on these pins can be misinterpreted as multiple edges and cause improper opera-
tion of the device. The PC board traces must be kept to a minimum distance or appropriately
terminated to ensure proper operation. If necessary, decoupling capacitors can be added on
these pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
1638F–DFLSH–09/02
11
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet AT45DB642.PDF ] | |
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