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PDF AK5358B Data sheet ( Hoja de datos )
| Número de pieza | AK5358B | |
| Descripción | 24-Bit ADC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK5358B]
AK5358B
96kHz 24-Bit ΔΣ ADC
GENERAL DESCRIPTION
The AK5358B is a stereo A/D Converter with a wide sampling rate range of 8kHz ∼ 96kHz and it is suitable
for consumer to professional audio system. The AK5358B achieves high accuracy and low cost by using
Enhanced dual bit ΔΣ techniques. No external components are required with single-ended analog inputs.
The audio interface has two formats (MSB justified, I2S) and can correspond to various systems like DTV,
DVR and AV Receiver.
FEATURES
Linear Phase Digital Anti-Alias Filtering
Single-ended Input
Digital HPF for DC-Offset cancel
S/(N+D): 92dB
DR:
102dB
S/N:
102dB
Sampling Rate Ranging from 8kHz to 96kHz
Master Clock:
256fs/384fs/512fs/768fs (8kHz ∼ 48kHz)
256fs/384fs
(48kHz ∼ 96kHz)
Input level: TTL/CMOS
Master / Slave Mode
Audio Interface: 24bit MSB justified / I2S selectable
Power Supply: 4.5 ∼ 5.5V (Analog), 2.7 ∼ 5.5V (Digital)
Ta = −20 ∼ 85°C
Small 16pin TSSOP Package
AK5357/59/81/58A Pin-compatible
VA VSS1 VD VSS2
MCLK
AINL
AINR
VCOM
ΔΣ
Modulator
ΔΣ
Modulator
Voltage Reference
Decimation
Filter
Decimation
Filter
Clock Divider
Serial I/O
Interface
LRCK
SCLK
SDTO
CKS2 CKS1 CKS0
PDN
DIF
MS1155-E-00
-1-
2010/02
1 page  
[AK5358B]
ANALOG CHARACTERISTICS
(Ta=25°C; VA=5.0, VD=5.0V; VSS1=VSS2=0V; fs=48kHz, 96kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data;
Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified)
Parameter
min typ max Units
ADC Analog Input Characteristics:
Resolution
Input Voltage
S/(N+D)
fs=48kHz
BW=20kHz
fs=96kHz
BW=40kHz
DR (−60dBFS, A-weighted)
S/N (A-weighted)
Input Resistance
fs=48kHz
fs=96kHz
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Power Supply Rejection
Power Supplies
(Note 4)
−1dBFS
−60dBFS
−1dBFS
−60dBFS
(Note 5)
2.7
82
-
-
-
94
94
13
9
90
-
24 Bits
3.0 3.3 Vpp
92 dB
39 dB
90 dB
38 dB
102 dB
102 dB
20 kΩ
14 kΩ
110 dB
0.1 0.5 dB
100 - ppm/°C
50 dB
Power Supply Current
Normal Operation (PDN pin = “H”)
VA 12 18
VD (fs=48kHz)
(Note 6)
35
VD (fs=96kHz)
(Note 7)
69
Power down mode (PDN pin = “L”)
(Note 8)
VA+VD
10 100
Note 4. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage.
Vin = 0.6 x VA (Vpp).
Note 5. PSR is applied to VA and VD with 1kHz, 50mVpp.
Note 6. VD=2mA@3V
Note 7. VD=4mA@3V
Note 8. All digital input pins and CKS1 pin are held VD or VSS2.
mA
mA
mA
μA
MS1155-E-00
-5-
2010/02
5 Page 
[AK5358B]
OPERATION OVERVIEW
■ System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency and master/slave modes are selected by CKS2-0 pins as shown in
Table 2.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
8.192MHz 12.288MHz 16.384MHz
11.2896MHz 16.9344MHz 22.5792MHz
12.288MHz 18.432MHz 24.576MHz
24.576MHz 36.864MHz
N/A
Table 1. System Clock Example
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
Mode
0
1
2
3
4
5
6
7
CKS2
L
L
L
L
H
H
H
H
CKS1
L
L
H
H
L
L
H
H
CKS0
L
H
L
H
L
H
L
H
Input Level Master/Slave
MCLK
CMOS
Slave
256/384fs (8k≤fs≤96k)
512/768fs (8k≤fs≤48k)
Reserved
CMOS
Master
256fs (8k≤fs≤96k)
CMOS
Master
512fs (8k≤fs≤48k)
TTL
Slave
256/385fs(∼ 96kHz)
512/768fs(∼ 48kHz)
Reserved
CMOS
Master
384fs (8k≤fs≤96k)
CMOS
Master
768fs (8k≤fs≤48k)
Table 2. Operation Mode Select
Note 15. SDTO outputs 16bit data at SCLK=32fs.
SCLK
≥ 48fs or 32fs
(Note 15)
64fs
64fs
≥ 48fs or 32fs
(Note 15)
64fs
64fs
MS1155-E-00
- 11 -
2010/02
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AK5358B.PDF ] | |
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