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PDF APW8868 Data sheet ( Hoja de datos )
| Número de pieza | APW8868 | |
| Descripción | DDR2 AND DDR3 SYNCHRONOUS BUCK CONTROLLER | |
| Fabricantes | ANPEC | |
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APW8868
DDR2 AND DDR3 SYNCHRONOUS BUCK CONTROLLER
WITH 1.5A LDO SUPPORT LOW IQ & DROOP
Features
Buck Controller (VDDQ)
• High Input Voltages Range from 3V to 28V Input
Power
• Provide Adjustable Output Voltage from 0.75V to
5.5V +1% Accuracy over Temperature
• Integrated MOSFET Drivers and Bootstrap Forward
P-CH MOSFET
• Low Quiescent Current (200µA)
• Excellent Line and Load Transient Responses
• PFM Mode for Increased Light Load Efficiency
• Constant On-Time Controller Scheme
- Switching Frequency Compensation for PWM
Mode
- Adjustable Switching Frequency from 100kHz to
550kHz in PWM Mode with DC Output Current
• S3 and S5 Pins Control The Device in S0, S3 or S4/
S5 State
• Power Good Monitoring
• Extra Droop Voltage Control Function with
Adjustable Current Setting
• 70% Under-Voltage Protection (UVP)
• 125% Over-Voltage Protection (OVP)
• Adjustable Current-Limit Protection
- Using Sense Low-Side MOSFET’s RDS(ON)
• TQFN-20 3mmx3mm Thin package
• Lead Free Available (RoHS Compliant)
+1.5A LDO Section (VTT)
• Sourcing or Sinking Current up to 1.5A
• Fast Transient Response for Output Voltage
• Output Ceramic Capacitors Support at least 10µF
MLCC
• VTT and VTTREF Track at Half the VDDQSNS by
internal divider
• +20mV Accuracy for VTT and VTTREF
• Independent Over-Current Limit (OCL)
• Thermal Shutdown Protection
General Description
The APW8868 integrates a synchronous buck PWM con-
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It offers the lowest total
solution cost in system where space is at a premium.
The APW8868 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
In Pulse Frequency Mode (PFM), the APW8868 provides
very high efficiency over light to heavy loads with loading-
modulated switching frequencies. On TQFN-20 Package,
the Forced PWM Mode works nearly at constant frequency
for low-noise requirements.
The APW8868 is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
prevents wrong operation during power on. Droop func-
tion is allowed to adjust output voltage during light load
period.
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
The output voltage of LDO tracks the voltage at VREF pin.
An internal resistor divider is used to provide a half volt-
age of VREF for VTTREF and VTT Voltage. The VTT output
voltage is only requiring 20µF of ceramic output capaci-
tance for stability and fast transient response. The S3
and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Dec., 2013
1
www.anpec.com.tw
1 page  
APW8868
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Symbol
VTT OUTPUT
Parameter
ILIM Current-Limit
RDS(ON) VTT Power MOSFETs RDS(ON)
IVTTLK VTT Leakage Current
IVTTSNSLK VTTSNS Leakage Current
IVTTDIS VTT Discharge Current
VTTREF OUTPUT
VVTTREF VTTREF Output Voltage
VTTREF Tolerance
IVTTREF VTTREF Source Current
IVTTREF VTTREF Sink Current
VDDQ OUTPUT
VVFB VFB Regulation Voltage
IDROOP
IOFFSET
VFB Input Current
VDDQ Discharge Current
DROOP Input Current
OFFSET Input Current
Test Conditions
Sourcing Current
(VIN=1.8V)
Sinking Current
(VIN=1.8V)
Sourcing Current
(VIN=1.5V)
Sinking Current
(VIN=1.5V)
TJ=25oC
TJ=125oC
TJ=25oC
TJ=125oC
TJ=25oC
TJ=125oC
TJ=25oC
TJ=125oC
Upper MOSFET
Lower MOSFET
VVTT = 1.25V, VS3 = 0V, VS5 = 5V,
TA = 25oC
VVTT = 1.25V, TA = 25oC
VVTT = 0.5V, VS3 = VS5 = 0V, TA = 25oC
VVREF = 0V
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2
-10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF
VLDOIN = VVTTREF =1.8V
-10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF
VLDOIN = VVDDQSNS = 1.5V
VVTTREF = 0V
VVTTREF = 1.8V
TA = 25 oC
TA = -40 oC to 85 oC
TA = 25 oC,
VVCC = 4.5V to 5.5V, VIN = 3V to 28V
TA = 25 oC,
Load = 0 to 10A, VVCC = 4.5V to 5.5V
VVFB= 0.78V
VS3 = VS5 = 0V, VVDDQSNS = 0.5V,
APW8868
Min Typ Max
Unit
1.8
1.6
-2
-1.6
1.6
1.1
-1.6
-1.1
-
-
-1.0
-1.00
15
2
-
-2.2
-
1.8
-
-1.8
-
350
350
-
0.01
25
3
-
-3
-
2.6
-
-2.6
-
500
500
1.0
1.00
35
A
A
mΩ
µA
µA
mA
- 0.9 -
- 0.75 -
V
-18 - +18
mV
-20 -
20
-10 -20 -40 mA
10 20
40 mA
0.745 0.75 0.755
0.7425 0.75 0.7575
V
V
-0.1 - +0.1 %
-1 - +1 %
-0.1 - +0.1 µA
15 25
- mA
- 5 - µA
- 5 - µA
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Dec., 2013
5
www.anpec.com.tw
5 Page 
APW8868
Function Description
The APW8868 integrates a synchronous buck PWM con-
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3 memory system in a
20-pin TQFN package. User defined output voltage is
also possible and can be adjustable from 0.75V to 5.5V.
Input voltage range of the PWM converter is 3V to 28V.
The converter runs an adaptive on-time PWM operation
at high-load condition and automatically reduces fre-
quency to keep excellent efficiency down to several mA.
The VTT LDO can source and sink up to 1.5A peak cur-
rent with only 10µF ceramic output capacitor. VTTREF
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
VTTREF within 20 mV at no load condition while 40 mV at
full load. The LDO input can be separated from VDDQ
and optionally connected to a lower voltage by using
VLDOIN pin. This helps reducing power dissipation in
sourcing phase. The APW8868 is fully compatible to
JEDEC DDR2/DDR3 specifications at S3/S5 sleep state
(see Table 1). When both VTT and VDDQ are disabled,
the non-tracking discharge mode discharges outputs
using internal discharge MOSFETs that are connected to
VDDQSNS and VTT.
Constant-On-Time PWM Controller with Input Feed-For-
ward
The constant on-time control architecture is a pseudo-
fixed frequency with input voltage feed-forward. This ar-
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
erator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
be more outstanding than a conventional constant on-
time controller which has large switching frequency varia-
tion over input voltage, output current and temperature.
Both in PFM and PWM, the on-time generator, which
senses input voltage on PHASE pin, provides very fast
on-time response to input line transients.
Another one-shot sets a minimum off-time (typical:
300ns). The on-time one-shot is triggered if the error com-
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
shot has timed out.
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
age on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
POR voltage threshold (4.3V typical), the POR signal goes
high and the chip initiates soft-start operations. Should
this voltage drop lower than 4.2V (typical), the POR dis-
ables the chip.
Soft- Start
The APW8868 integrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
regulation set point at a predictable slew rate. The slew
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
start process. The figure 1 shows VDDQ soft-start
sequence. When the S5 pin is pulled above the rising S5
threshold voltage, the device initiates a soft-start process
to ramp up the output voltage. The soft-start interval is 1.
2ms (typical) and independent of the UGATE switching
frequency.
2ms
VCC and VPVCC
1.2ms
VOUT
S5
VPGOOD
Fig1. Soft-Start Sequence
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Dec., 2013
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet APW8868.PDF ] | |
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