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Número de pieza | ML610421 | |
Descripción | 8-bit Microcontroller | |
Fabricantes | LAPIS | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ML610421 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! ML610421
8-bit Microcontroller with a Built-in LCD driver
FEDL610421-02
Issue Date: Feb.9, 2015
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit
successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe
line architecture parallel procesing. This LSI operates in both high/low-speed mode and power-saving mode, it is most
suitable for battery operated products.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
0.24 4µs (@4.096 MHz system clock)
• Internal memory
− Internal 32KBbyte mask ROM (16K×16 bits) (including unusable 1KByte TEST area)
− Internal 1KByte Data RAM (1024×8 bits), 1KByte Display Allocation RAM (1024 x 8bit)
− Internal 100Byte RAM for display
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 20 maskable interrupt sources (Internal sources: 16, External sources: 4)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
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1 page BLOCK DIAGRAM
ML610421 Block Diagram
Figure 1 show the block diagram of the ML610421.
"*" indicates the secondary function of each port.
FEDL610421-02
ML610421
VDD
VSS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
VDDL
VDDX
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
AVDD
AVSS
VREF
AIN0, AIN1
EPSW1~3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100)
GREG
0~15
ELR1~3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
RESET &
TEST
OSC
Power
INT
1
RC-ADC
×2
RAM
1024byte
Interrupt
Controller
INT
1
WDT
INT
4
TBC
INT
1
1kHzTC
Capture
×2
INT
4 8bit Timer
×4
ECSR1~3
DSR/CSR
PC
BUS
Controller
Program
Memory
(mask ROM)
32Kbyte
INT
1
SSIO
INT
1
UART
INT
1
I2C
INT
1
PWM
INT
1
Melody
INT
5
GPIO
12bit-ADC
INT
1
Display Allocation
RAM 1024Byte
LCD
Driver
BLD
Display RAM
100Byte
LCD
BIAS
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
SDA*
SCL*
PWM0*
MD0*
NMI
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
PA0 to PA7
COM0 to COM7
SEG0 to SEG49
VL1, VL2, VL3, VL4
C1, C2, C3, C4
Figure 1 ML610421 Block Diagram
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5 Page PAD NO.
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82
83
84
85
86
87
88
Primary function
Pin name I/O
Function
SEG42 O LCD segment pin
SEG43 O LCD segment pin
SEG44 O LCD segment pin
SEG45 O LCD segment pin
SEG46 O LCD segment pin
SEG47 O LCD segment pin
SEG48 O LCD segment pin
SEG49 O LCD segment pin
Secondary function
Pin name I/O
Function
FEDL610421-02
ML610421
Tertiary function
Pin name I/O
Function
11/31
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet ML610421.PDF ] |
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