PDF PI6C49021B Data sheet ( Hoja de datos )

Número de pieza	PI6C49021B
Descripción	Low Power High Integration Clock Generator
Fabricantes	Pericom Semiconductor
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Hay una vista previa y un enlace de descarga de PI6C49021B (archivo pdf) en la parte inferior de esta página. Total 12 Páginas
No Preview Available ! PI6C49021B Low Power High Integration Clock Generator Features ÎÎ3.3V supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎOutput àà 3 x low power PCIe 2.0 100MHz clock with integrate series termination resistor àà 2 x 66.667MHz LVCMOS clock for CPU àà 1 x 125MHz LVCMOS clock for Gigabit Ethernet àà 2 x 50MHz LVCMOS clock for CPLD àà 3 x 25MHz LVCMOS clock for Ethernet PHY àà 2 x 25MHz low jitter LVPECL Ethernet clock àà 1 x 24MHz LVCMOS for USB PHY ÎÎPackaging (Pb free and Green) àà 48-pin TQFN Description The new PI6C49021B is a high integration clock generator intended for all kinds of embedded applications and networking application with PCIe interface. The device is the most cost effective way to generate multi-frequencies and multi-outputs clocks from a 25MHz crystal and reference clock. The device can generate 100MHz HCSL clock, single-ended clocks includes 24MHz, 25MHz, 50HMz, 125HMz, and low jitter 25MHz LVPECL clock. Block Diagram 25MHz XTAL or clock input X1 X2 OE_PCIE OE_PECL SCLK SDATA KA T Crystal Oscillator 3 PLL Clock Synthesis & Control Circuit 2 2 3 I2C Control Circuit 2 PCIE(0-2) SE_66M(0~1) SE_125M SE_50M(0~1) SE_25M(0,2) 2) SE_24M PECL_25M(0~1) All trademarks are property of their respective owners. 15-0042 1 www.pericom.com 03/31/15 1 page PI6C49021B Low Power High Integration Clock Generator Byte 0: Bit 6 and Bit 5 Functionality Bit Bit 5 Description 0 X RESET# = "H" will enable all outputs; SMBus can not control each output. 10 Disable all outputs and tri-states the outputs. When pin 18 (RESET#) is set low, force device to power-on reset and set all registers to default values. 11 Enable outputs according to the SMBus default values; SMBus can control each output. When pin 18 (RE- SET#) is set low, force to power-on reset and set all registers to default values. Byte 1: Control Register Bit Description 7 OE for SE_125M 6 OE for SE_50M0 5 OE for SE_50M1 4 OE for SE_25M0 3 OE for SE_25M1 2 OE for SE_24M 1, 0 Reserved Type RW RW RW RW RW RW Power Up Condi- tion Output(s) Affected 1 SE_125M 1 SE_50M0 1 SE_50M1 1 SE_25M0 1 SE_25M1 1 Undefined SE_24M Not Applicable Notes 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled Byte 2: Control Register Bit Description 7 to 0 Reserved Type R Power Up Condi- tion Output(s) Affected Undefined Not Applicable Notes All trademarks are property of their respective owners. 15-0042 5 www.pericom.com 03/31/15 5 Page PI6C49021B Low Power High Integration Clock Generator Configuration test load board termination for HCSL Outputs PI6C49021B Rs 33Ω 5% Rs 33Ω 5% TLA TLB 2pF 5% Clock Clock# 2pF 5% Figure 4. Configuration Test Load Board Termination VDD Zo = 50Ω L = 0 ~ 18 in. 150Ω Zo = 50Ω 150Ω Figure 5. LVPECL output termination 100Ω All trademarks are property of their respective owners. 15-0042 11 www.pericom.com 03/31/15 11 Page

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