PDF PI6C49021 Data sheet ( Hoja de datos )

Número de pieza	PI6C49021
Descripción	Low Power High Integration Clock Generator
Fabricantes	Pericom Semiconductor
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No Preview Available ! PI6C49021 Low Power High Integration Clock Generator Features ÎÎ3.3V supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎOutput àà 3 x low power PCIe 2.0 100MHz clock with spread spectrum support and integrate series termination resistor àà 2 x 66.667MHz LVCMOS clock for CPU àà 1 x 125MHz LVCMOS clock for Gigabit Ethernet àà 2 x 50MHz LVCMOS clock for CPLD àà 3 x 25MHz LVCMOS clock for Ethernet PHY àà 2 x 25MHz low jitter LVPECL Ethernet clock àà 1 x 24MHz LVCMOS for USB PHY ÎÎPackaging (Pb free and Green) àà 48-pin TQFN Description The new PI6C49021 is a high integration clock generator intended for all kinds of embedded applications and networking application with PCIe interface. The device is the most cost effective way to generate multi-frequencies and multi-outputs clocks from a 25MHz crystal and reference clock. The device can generate 100MHz HCSL clock, single-ended clocks includes 24MHz, 25MHz, 50HMz, 125HMz, and low jitter 25MHz LVPECL clock. Block Diagram 25MHz XTAL or clock input X1 X2 OE_PCIE OE_PECL SCLK SDATA KA T Crystal Oscillator 3 PLL Clock Synthesis & Spread Spectrum & Control Circuit 2 2 3 I2C Control Circuit 2 PCIE(0-2) SE_66M(0~1) SE_125M SE_50M(0~1) SE_25M(0,2) 2) SE_24M PECL_25M(0~1) 13-0015 1 www.pericom.com P-0.1 02/27/13 1 page PI6C49021 Low Power High Integration Clock Generator Serial Data Interface (SMBus) PI6C49021 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad- dress and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits Start bit D2H Ack Register offset Ack Byte Count = N Ack Data Byte 0 Ack … Data Byte N-1 Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 1 Ack 1 bit Stop bit How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits S: M: send M: M: S: starting Start Send sends databyte bit "D2h" Ack location: N S: sends Ack M: Start bit M: Send "D3h" S: sends Ack sends # of data bytes that will be sent: M: sends Ack S: sends start- ing data byte N X 1 bit M: sends Ack … … 8 bits S: sends data byte N+X- 1 1 bit M: Not Ac- knowl- edge 1 bit M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description 7 OE for SE_66M0 6 Enable hardware or software control of OE bits (see Byte 0-Bit 6 and Bit 5 Functionality table) Software RESET# bit. Enablea or disables all 5 outputs. (see Byte 0-Bit 6 and Bit 5 Functionality table) 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 OE for SE_66M1 Type RW RW RW R R R R RW Power Up Condition 1 Output(s) Affected SE_66M0 output 0 All outputs 1 All outputs Undefined Undefined Undefined Undefined 1 Not applicable SE_66M1 output Notes 0 = disabled 1 = enabled 0 = hardware cntl 1 = software ctrl 0 = disabled 1 = enabled 0 = disabled 1 = enabled All trademarks are property of their respective owners. 13-0015 5 www.pericom.com P-0.1 02/27/13 5 Page PI6C49021 Low Power High Integration Clock Generator Notes (Continued) 6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation. 8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–. 9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. 10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread. Electrical Characteristics - 25MHz LVPECL outputs Parameter Cycle Time Min Typ - 40 Duty Cycle 45 - Rise/Fall Time (20%-80%) 0.3 - RMS Jitter (12kHz-5 MHz) Clock Tolerance (25MHz) Output High Voltage Output Low Voltage Peak to Peak Output Voltage Swing - -50 VDD-1.4 VDD-2.0 0.6 - - Max - 55 0.6 2 (spur off) +50 VDD-0.9 VDD-1.7 1.0 Unit ns % ns ps-RMS ppm V All trademarks are property of their respective owners. 13-0015 11 www.pericom.com P-0.1 02/27/13 11 Page

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