PDF PI6C49004 Data sheet ( Hoja de datos )

Número de pieza	PI6C49004
Descripción	Networking Clock Generator
Fabricantes	Pericom Semiconductor
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Hay una vista previa y un enlace de descarga de PI6C49004 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas
No Preview Available ! PI6C49004 Networking Clock Generator Features • 3.3V +/-10% Supply Voltage • Uses 25MHz xtal such as Saronix-eCera™ SRX7278 • Twelve PCIe® 100MHz outputs with optional -0.5% spread spectrum support • Two LVCMOS 50MHz outputs that support +/- 10% frequency margining • One frequency selectable 33/66/133MHz LVCMOS output • One 32.256MHz LVCMOS output • Industrial temperature -40°C to 85°C • Package: 56-pin TSSOP package Description The PI6C49004 is a clock generator device intended for PCIe®/ networking applications. The device includes twelve 100MHz differential Host Clock Signal Level (HCSL) outputs for PCIe, two single-ended 50MHz outputs, one single-ended 32.256MHz output, and one selectable single-ended 33/66/133MHz output. Using a serially programmable SMBUS interface, the PI6C49004 incorporates spread spectrum modulation on the twelve 100MHz HCSL PCIe outputs, and independent frequency margining on the 50MHz output, 33.3333MHz and 66.6666MHz clock outputs. Pin Configuration Block Diagram 25 MHz crystal or clock input Clock Buffer/ Crystal Oscillator VDD 12 SCLK SDATA PD_RESET PLL, Dividers, Buffers, and Logic 12 100M_OUT(0-11) 2 50M_OUT(1-2) 33/66/133M_OUT1 32.256M_OUT1 8 GND ISET 475 Ohms 1% VDD IREF NC 100M_Q11- 100M_Q11+ 100M_Q10- 100M_Q10+ VDD VDD GND 100M_Q9- 100M_Q9+ 100M_Q8- 100M_Q8+ 100M_Q7- 100M_Q7+ SCLK SDATA GND 50M_OUT1 50M_OUT2 VDD GND VDD 32.256M_OUT1 GND NC PD_RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 11-0080 09-0098 1 56 GND 55 VDD 54 100M_Q0- 53 100M_Q0+ 52 100M_Q1+ 51 100M_Q1- 50 VDD 49 GND 48 VDD 47 100M_Q2+ 46 100M_Q2- 45 100M_Q3+ 44 100M_Q3- 43 100M_Q4+ 42 100M_Q4- 41 100M_Q5+ 40 100M_Q5- 39 VDD 38 GND 37 VDD 36 100M_Q6+ 35 100M_Q6- 34 33/66/133M_OUT1 33 VDD 32 GND 31 VDD 30 X2 29 X1 PS9047A 04/11/11 1 page PI6C49004 Networking Clock Generator Byte 0 - Bit 6 and Bit 5 Functionality Bit 6 Bit 5 Description 0 X PD_RESET HW pin/signal = enabled 1 0 Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE 1 1 Enable all outputs, PD_RESET HW pin/signal = DON'T CARE Byte 1: Control Register Bit Description 7 OE for 32.256M_Out1 6 OE for 50M_Out1 5 OE for 33/66/133M_Out1 4 OE for 100M_Q11 HCSL output 3 OE for 100M_Q10 HCSL output 2 OE for 100M_Q09 HCSL output 1 OE for 100M_Q08 HCSL output 0 OE for 100M_Q07 HCSL output Type RW RW RW RW RW RW RW RW Power Up Condi- tion Output(s) Affected 1 32.256M_Out1 1 50M_Out1 1 33/66/133M_Out1 1 100M_Q11 0 100M_Q10 0 100M_Q9 0 100M_Q8 0 100M_Q7 Notes 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled Byte 2: Control Register Bit Description Type 7 6 5 4 to 0 Frequency margining select bit FS6 Frequency margining select bit FS5 Frequency margining select bit FS4 Reserved RW RW RW R Power Up Condi- tion Output(s) Affected 1 0 33/66/133M_Out1 0 Undefined Not Applicable Notes See 33/66/133MHz Frequency Margin- ing Table on Page 3 11-0080 09-0098 5 PS9047A 04/11/11 5 Page Configuration test load board termination for HCSL Outputs PI6C49004 Networking Clock Generator PI6C49004 Rs 33Ω 5% Rs 33Ω 5% 475Ω 1% Rp 49.9Ω 1% TLA Rp 49.9Ω 1% TLB 2pF 5% Clock Clock# 2pF 5% Figure 4. Configuration Test Load Board Termination 11-0080 09-0098 11 PS9047A 04/11/11 11 Page

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