PDF PI6C49003A Data sheet ( Hoja de datos )

Número de pieza	PI6C49003A
Descripción	Gen 2 Networking Clock Generator
Fabricantes	Pericom Semiconductor
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No Preview Available ! PI6C49003A PCIe® Gen 2 Networking Clock Generator Features • 3.3V +/-10% Supply Voltage • Uses 25MHz xtal • Five PCIe® Gen. 2 100MHz HCSL outputs with optional -0.5% spread spectrum support • Two LVCMOS 50MHz outputs that support +/- 10% frequency margining • One frequency selectable 33/66/133MHz LVCMOS output • One 32.256MHz LVCMOS output • Industrial temperature -40°C to 85°C • Package: 48-pin TSSOP package Description The PI6C49003A is a clock generator device intended for PCIe® Gen2 networking applications. The device includes five 100MHz differential Host Clock Signal Level (HCSL) outputs for PCIe Gen 2, two single-ended 50MHz outputs, one single-ended 32.256MHz output, and one selectable single-ended 33/66/133MHz output. Using a serially programmable SMBUS interface, the PI6C49003A incorporates spread spectrum modulation on the twelve 100MHz HCSL PCIe Gen 2 outputs, and independent frequency margining on the 50MHz output, 33.3333MHz and 66.6666MHz clock outputs. Block Diagram 25 MHz crystal or clock input Clock Buffer/ Crystal Oscillator VDD 14 SCLK SDATA PD_RESET PLL, Dividers, Buffers, and Logic 5 10 GND ISET 475 Ohms 1% Pin Configuration 100M_OUT(0-4) 50M_OUT(1-2) 33/66/133M_OUT1 32.256M_OUT1 VDD IREF NC NC VDD VDD GND GND VDD GND VDD SCLK SDATA GND 50M_Out1 50M_Out2 VDD GND VDD 32.256M_Out1 GND NC NC PD_RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 GND 47 VDD 46 100M_Q0- 45 100M_Q0+ 44 100M_Q1+ 43 100M_Q1- 42 VDD 41 GND 40 VDD 39 100M_Q2+ 38 100M_Q2- 37 100M_Q3+ 36 100M_Q3- 35 VDD 34 GND 33 VDD 32 100M_Q4+ 31 100M_Q4- 30 33/66/133M_Out1 29 VDD 28 GND 27 VDD 26 X2 25 X1 All trademarks are property of their respective owners. 14-0198 1 www.pericom.com 11/11/14 1 page PI6C49003A PCIe® Gen 2 Networking Clock Generator Serial Data Interface (SMBus) PI6C49003A is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad- dress and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits Start bit D2H Ack Register offset Ack Byte Count =N Ack Data Byte 0 Ack … Data Byte N-1 Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 1 Ack 1 bit Stop bit How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit … 8 bits 1 bit 1 bit M: Start bit M: Send "D2h" S: sends Ack M: send starting databyte location: N S: sends Ack M: Start bit M: Send "D3h" S: sends Ack S: sends # of data bytes that will be sent: X M: sends Ack S: sends start- ing data byte N M: sends Ack … S: sends data byte N+X-1 M: Not Ac- knowl- edge M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description Type 7 Spread Spectrum Selection for 100MHz HCSL PCI- Express clocks RW 6 Enables hardware or software control of OE bits (see Byte 0–Bit 6 and Bit 5 Functionality table) RW Software PD_RESET bit. Enables or disables all out- 5 puts RW (see Byte 0–Bit 6 and Bit 5 Functionality table) 4 Frequency margining select bit FS3 RW 3 Frequency margining select bit FS2 2 Frequency margining select bit FS1 RW RW 1 Frequency margining select bit FS0 RW 0 OE for single-ended 50MHz output 50M_Out2 RW Power Up Condition 0 Output(s) Affected All 100MHz HCSL PCI Express outputs 0 PD_RESET pin, bit 5 Notes 0=spread off 1 = -0.5% down spread 0 = hardware cntl 1 = software ctrl 1 All outputs 0 = disabled 1 = enabled 1 0 1 50M_Out1 and 50M_ Out2 See 50MHz Frequency Margining Table on Page 3 0 1 Single-ended 50MHz output 50M_Out2 0 = disabled 1 = enabled All trademarks are property of their respective owners. 14-0198 5 www.pericom.com 11/11/14 5 Page PI6C49003A PCIe® Gen 2 Networking Clock Generator Crystal Load Capacitors If an input crystal is used, crystal should be connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. CL = Crystal's load capacitance in pF Crystal Capacitors (pF) = (CL - 8) 2 For example, for a crystal with a 18pF load cap, each external crystal cap would be 18pF. (18 - 8) 2 =18. Application Notes Crystal circuit connection The following diagram shows PI6LC4830-01 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggest- ed to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit SaRonix-eCera CG2500003 C1 27pF Crystal�(CL�=�18pF) XTAL_IN C2 33pF XTAL_OUT Recommended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf Configuration test load board termination for HCSL Outputs PI6C49003A Rs 33Ω 5% Rs 33Ω 5% 475Ω 1% Rp 49.9Ω 1% TLA Rp 49.9Ω 1% TLB 2pF 5% Clock Clock# 2pF 5% Figure 4. Configuration Test Load Board Termination All trademarks are property of their respective owners. 14-0198 11 www.pericom.com 11/11/14 11 Page

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