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PDF PI4MSD5V9547 Data sheet ( Hoja de datos )
| Número de pieza | PI4MSD5V9547 | |
| Descripción | 8 Channel I2C bus multiplexer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI4MSD5V9547 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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PI4MSD5V9547
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8 Channel I2C bus multiplexer with Reset
Features
1-of-8 bidirectional translating multiplexer
I2C-bus interface logic
Operating power supply voltage from 1.65V to
5.5V
Allows voltage level translation between 1.2V,
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Active LOW reset input
Channel selection via I2C bus
Power-up with one channel on
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22-
A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
JESD78 which exceeds 100 mA
Packages offered: TSSOP-24L,TQFN-24ZD
Description
The PI4MSD5V9547 is an octal bidirectional
translating multiplexer controlled by the I2C-bus. The
SCL/SDA upstream pair fans out to eight downstream
pairs, or channels.
Only one SCx/SDx channel can be selected at a time,
determined by the contents of the programmable control
register. The device powers up with Channel 0
connected, allowing immediate communication between
the master and downstream devices on that channel.
An active LOW reset input allows the
PI4MSD5V9547 to recover from a situation where one
of the downstream I2C-buses is stuck in a LOW state.
Pulling the RESET pin LOW resets the I2C-bus state
machine and causes all the channels to be deselected as
does the internal Power-On Reset (POR) function.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum high
voltage which is passed by the PI4MSD5V9547. This
allows the use of different bus voltages on each pair, so
that1.2V, 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired
voltage level for each channel. All I/O pins are 5 V
tolerant.
Pin Configuration
TSSOP
TQFN
2015-07-0040
PT0544-2
8/18/15
1
1 page  
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
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AC Electrical characteristics
Tamb = - 40 ºC to +85 ºC; unless otherwise specified.
Symbol Parameter
Conditions
VCC
Min Typ
tPD[1]
propagation delay
from SDA to SDx,
or SCL to SCx
1.65V to 5.5V
RESET
tw(rst)L LOW-level reset time
1.65V to 5.5V
4
trst reset time
SDA clear
1.65V to 5.5V
500
tREC;STA
recovery time to START
condition
1.65V to 5.5V
0
Note
[1]Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15 pF load capacitance.
Max
0.3
Unit
ns
ns
ns
ns
I2C Interface Timing Requirements
Symbol
fscl
tLow
tHigh
tSP
tSU:DAT
tHD:DAT
tr
tf
tBUF
tSU:STA
tHD:STA
tSU:STO
tVD:DAT
tVD:ACK
Cb
Parameter
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
Valid-data time (high to low) [2]
SCL low to SDA output low valid
Valid-data time (low to high) [2]
SCL low to SDA output high valid
Valid-data time of ACK condition
ACK signal from SCL low to SDA output low
I2C bus capacitive load
STANDARD MODE
I2C BUS
MIN MAX
0 100
4.7
4
50
250
0 [1]
1000
300
4.7
4.7
4
4
1
0.6
1
400
FAST MODE
I2C BUS
UNIT
MIN MAX
0 400 kHz
1.3 μs
0.6 μs
50 ns
100 ns
0 [1] μs
300 ns
300 ns
1.3 μs
0.6 μs
0.6 μs
0.6 μs
1 μs
0.6 μs
1 μs
400 pF
Notes:
[1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL
signal), in order to bridge the undefined region of the falling edge of SCL.
[2] Data taken using a 1-kΩ pull up resistor and 50-pF load Notes
2015-07-0040
PT0544-2
8/18/15
5
5 Page 
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
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Data is transmitted to the PI4MSD5V9547 control register using the write mode shown in bellow
Figure 11. Write Control Register
Data is transmitted to the PI4MSD5V9547 control register using the write mode shown in bellow
Figure 12. Read Control Register
2015-07-0040
PT0544-2
8/18/15
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI4MSD5V9547.PDF ] | |
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