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PDF PI4MSD5V9543B Data sheet ( Hoja de datos )
| Número de pieza | PI4MSD5V9543B | |
| Descripción | 2 Channel I2C bus switch | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI4MSD5V9543B
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2 Channel I2C bus switch with interrupt logic and Reset
Features
1-of-2 bidirectional translating multiplexer
I2C-bus interface logic
Operating power supply voltage:1.65 V to 5.5 V
Allows voltage level translation between 1.2V,
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Channel selection via I2C bus
Power-up with all multiplexer channels deselected
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22-
A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
JESD78 which exceeds 100 mA
Packages offered: SOIC-14W,TSSOP-14L
the contents of the programmable control register. Two
interrupt inputs, INT0 and INT1, one for each of the
downstream pairs, are provided. One interrupt output,
INT, which acts as an AND of the two interrupt inputs,
is provided.
An active LOW reset input allows the
PI4MSD5V9543B to recover from a situation where one
of the downstream buses is stuck in a LOW state.
Pulling the RESET pin LOW resets the I2C bus state
machine and causes all the channels to be deselected, as
does the internal power-on reset function.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum high
voltage which will be passed by the PI4MSD5V9543X.
This allows the use of different bus voltages on each
SCx/SDx pair, so that 1.2V,1.8 V, 2.5 V, or 3.3 V parts
can communicate with 5 V parts without any additional
protection. External pull-up resistors pull the bus up to
the desired voltage level for each channel.
All I/O pins are 5 V tolerant.
The PI4MSD5V9543A and PI4MSD5V9543B are
identical except for the fixed portion of the slave address.
Pin Configuration
Pin Description
Pin
No
Pin
Name
Type
Description
1 A0 Input address input 0
2 A1 Input address input 1
TSSOP14
SOP14
Description
The PI4MSD5V9543B is a bidirectional translating
switch, controlled by the I2C bus. The SCL/SDA
upstream pair fans out to two downstream pairs, or
channels. Any individual SCx/SDx channels or
combination of channels can be selected, determined by
3 RESET Input active LOW reset input
4 INT0 Input active LOW interrupt input 0
5 SD0 I/O serial data 0
6 SC0 I/O serial clock 0
7 GND Ground supply ground
8 INT1 Input active LOW interrupt input 1
9 SD1 I/O serial data 1
10 SC1 I/O serial clock 1
11 INT Output active LOW interrupt output
12 SCL I/O serial clock line
13 SDA I/O serial data line
14 VCC Power supply voltage
2015-07-0038
PT0535-4 8/18/15
1
1 page  
PI4MSD5V9543B
2 Channel I2C bus switch
with Interrupt Logic and Reset
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I2C Interface Timing Requirements
Symbol
fscl
tLow
tHigh
tSP
tSU:DAT
tHD:DAT
tr
tf
tBUF
tSU:STA
tHD:STA
tSU:STO
tVD:DAT
tVD:ACK
Cb
Parameter
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
Valid-data time (high to low) [2]
SCL low to SDA output low valid
Valid-data time (low to high) [2]
SCL low to SDA output high valid
Valid-data time of ACK condition
ACK signal from SCL low to SDA output low
I2C bus capacitive load
STANDARD MODE
I2C BUS
MIN MAX
0 100
4.7
4
50
250
0 [1]
1000
300
4.7
4.7
4
4
1
0.6
1
400
FAST MODE
I2C BUS
UNIT
MIN MAX
0 400 kHz
1.3 μs
0.6 μs
50 ns
100 ns
0 [1] μs
300 ns
300 ns
1.3 μs
0.6 μs
0.6 μs
0.6 μs
1 μs
0.6 μs
1 μs
400 pF
Notes:
[1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL
signal), in order to bridge the undefined region of the falling edge of SCL.
[2] Data taken using a 1-kΩ pull up resistor and 50-pF load Notes
Figure 2. Definition of timing on the I2C-bus
2015-07-0038
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PT0535-4 8/18/15
5 Page 
PI4MSD5V9543B
2 Channel I2C bus switch
with Interrupt Logic and Reset
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A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master
to generate a STOP condition.
Figure 10. Acknowledgment on I2C Bus
Data is transmitted to the PI4MSD5V9543B control register using the write mode shown in bellow
Figure 11. Write Control Register
Data is transmitted to the PI4MSD5V9543B control register using the write mode shown in bellow
Figure 12. Read Control Register
2015-07-0038
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PT0535-4 8/18/15
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI4MSD5V9543B.PDF ] | |
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